1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust Data Sheet AD9508 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.65 GHz differential clock inputs/outputs OUT0 10-bit programmable dividers, 1 to 1024, all integers AD9508 DIV/ OUT0 Up to 4 differential outputs or 8 CMOS outputs CLK OUT1 Pin strapping capability for hardwired programming at DIV/ CLK OUT1 power-up OUT2 <115 fs rms broadband random jitter (see Figure 25) DIV/ OUT2 Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz) OUT3 DIV/ Excellent output-to-output isolation SCLK/SCL/S0 OUT3 CONTROL SDIO/SDA/S1 Automatic synchronization of all outputs INTERFACE 2 SDO/S3 SPI/I C/PINS Single 2.5 V/3.3 V power supply CS/S2 Internal LDO (low drop-out) voltage regulator for enhanced power supply immunity Phase offset select for output-to-output coarse delay adjust PIN CONTROL RESET SYNC 3 programmable output logic levels, LVDS, HSTL, and CMOS Figure 1. 2 Serial control port (SPI/I C) or pin-programmable mode Space-saving 24-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that Each output has a programmable divider that can be bypassed emphasizes low jitter to maximize system performance. This or be set to divide by any integer up to 1024. In addition, the device benefits applications like clocking data converters with AD9508 supports a coarse output phase adjustment between demanding phase noise and low jitter requirements. the outputs. There are four independent differential clock outputs, each with The device can also be pin programmed for various fixed 2 various types of logic levels available. Available logic types configurations at power-up without the need for SPI or I C include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS programming. (250 MHz). In 1.8 V CMOS output mode, the differential output The AD9508 is available in a 24-lead LFCSP and operates from becomes two CMOS single-ended signals. The CMOS outputs a either a single 2.5 V or 3.3 V supply. The temperature range is are 1.8 V logic levels, regardless of the operating supply voltage. 40C to +85C. Rev. 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Technical Support www.analog.com 11161-001AD9508 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input.................................................................................. 23 Applications ....................................................................................... 1 Clock Outputs ............................................................................. 24 Functional Block Diagram .............................................................. 1 Clock Dividers ............................................................................ 24 General Description ......................................................................... 1 Phase Delay Control .................................................................. 24 Revision History ............................................................................... 3 Reset Modes ................................................................................ 25 Specifications ..................................................................................... 4 Power-Down Mode .................................................................... 25 Electrical Characteristics ............................................................. 4 Output Clock Synchronization ................................................. 25 Power Supply Current and Temperature Conditions .............. 4 Power Supply ............................................................................... 25 Clock Inputs and Output DC Specifications ............................ 5 Thermally Enhanced Package Mounting Guidelines ............ 25 Output Driver Timing Characteristics ...................................... 6 Pin Strapping to Program on Power-Up ..................................... 26 Logic Inputs ................................................................................... 7 Serial Control Port ......................................................................... 27 2 Serial Port SpecificationsSPI Mode ........................................ 7 SPI/I C Port Selection ................................................................ 27 2 Serial Port SpecificationsI C Mode ........................................ 8 SPI Serial Port Operation .......................................................... 27 2 External Resistor Values For Pin Strapping Mode ................... 9 I C Serial Port Operation .......................................................... 30 Clock Output Additive Phase Noise .......................................... 9 Register Map ................................................................................... 33 Clock Output Additive Time Jitter ........................................... 10 Register Map Bit Descriptions ...................................................... 34 Absolute Maximum Ratings .......................................................... 11 Serial Port Configuration (Register 0x00) .............................. 34 Thermal Characteristics ............................................................ 11 Silicon Revision (Register 0x0A to Register 0x0D) ............... 34 ESD Caution ................................................................................ 11 Chip Level Functions (Register 0x12 to Register 0x14) ........ 34 Pin Configuration and Function Descriptions ........................... 12 OUT0 Functions (Register 0x15 to Register 0x1A) ............... 35 Typical Performance Characteristics ........................................... 14 OUT1 Functions (Register 0x1B to Register 0x20) ............... 36 Test Circuits ..................................................................................... 20 OUT2 Functions (Register 0x21 to Register 0x26) ................ 37 Input/Output Termination Recommendations ...................... 20 OUT3 Functions (Register 0x27 to Register 0x2C) ............... 38 Terminology .................................................................................... 21 Packaging and Ordering Information ......................................... 40 Theory of Operation ...................................................................... 22 Outline Dimensions ................................................................... 40 Detailed Block Diagram ............................................................ 22 Ordering Guide .......................................................................... 40 Programming Mode Selection .................................................. 22 Rev. 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