800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet AD9513 FEATURES FUNCTIONAL BLOCK DIAGRAM RSET VSGND 1.6 GHz differential clock input 3 programmable dividers LVDS/CMOS AD9513 Divide-by in range from1 to 32 OUT0 /1 . /32 Phase select for coarse delay adjust OUT0B Three 800 MHz/250 MHz LVDS/CMOS clock outputs LVDS/CMOS Additive output jitter 300 fs rms CLK OUT1 Time delays up to 11.6 ns /1 . /32 Device configured with 4-level logic pins CLKB OUT1B Space-saving, 32-lead LFCSP LVDS/CMOS SYNCB APPLICATIONS OUT2 /1 . /32 t Low jitter, low phase noise clock distribution OUT2B Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers SETUP LOGIC High performance instrumentation Broadband infrastructure VREF S10 S9S8S7S6S5S4S3S2S1 S0 ATE Figure 1. GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a One of the outputs features a delay element with three design that emphasizes low jitter and phase noise to maximize selectable full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), data converter performance. Other applications with each with 16 steps of fine adjustment. demanding phase noise and jitter requirements also benefit The AD9513 does not require an external controller for from this part. operation or setup. The device is programmed by means of There are three independent clock outputs that can be set to 11 pins (S0 to S10) using 4-level logic. The programming pins either LVDS or CMOS levels. These outputs operate to are internally biased to V . The VREF pin provides a level of S 800 MHz in LVDS mode and to 250 MHz in CMOS mode. V . V (3.3 V) and GND (0 V) provide the other two logic levels. S S Each output has a programmable divider that can be set to The AD9513 is ideally suited for data converter clocking divide by a selected set of integers ranging from 1 to 32. The applications where maximum converter performance is phase of one clock output relative to the other clock output can achieved by encode signals with subpicosecond jitter. be set by means of a divider phase select function that serves as The AD9513 is available in a 32-lead LFCSP and operates from a coarse timing adjustment. a single 3.3 V supply. The temperature range is 40C to +85C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20052020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 05595-001AD9513 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-On SYNC .................................................................... 17 Applications ...................................................................................... 1 SYNCB ..................................................................................... 17 Functional Block Diagram .............................................................. 1 RSET Resistor ............................................................................. 18 General Description ......................................................................... 1 VREF ............................................................................................ 18 Revision History ............................................................................... 2 Setup Configuration .................................................................. 18 Specifications .................................................................................... 3 Divider Phase Offset .................................................................. 20 Clock Input ................................................................................... 3 Delay Block ................................................................................. 21 Clock Outputs ............................................................................... 3 Outputs ........................................................................................ 21 Timing Characteristics ................................................................ 4 Power Supply .............................................................................. 22 Clock Output Phase Noise .......................................................... 6 Exposed Metal Paddle ........................................................... 22 Clock Output Additive Time Jitter ............................................ 8 Power Management ................................................................... 22 SYNCB, VREF, and Setup Pins .................................................. 9 Applications Information ............................................................. 23 Power ............................................................................................. 9 Using the AD9513 Outputs for ADC Clock Applications ... 23 Timing Diagrams ............................................................................ 10 LVDS Clock Distribution.......................................................... 23 Absolute Maximum Ratings ......................................................... 11 CMOS Clock Distribution ........................................................ 23 1 Thermal Characteristics ........................................................... 11 Setup Pins (S0 to S10) ................................................................ 24 Pin Configuration and Function Descriptions .......................... 12 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 24 Terminology .................................................................................... 13 Phase Noise and Jitter Measurement Setups .......................... 25 Typical Performance Characteristics ........................................... 14 Outline Dimensions ....................................................................... 26 Functional Description .................................................................. 17 Ordering Guide .......................................................................... 26 Overall .......................................................................................... 17 CLK, CLKBDifferential Clock Input ................................... 17 Synchronizatio n .......................................................................... 17 REVISION HISTORY 11/2020Rev. B to Rev. C 1/2017Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Figure 5 and Table 9 .................................................. 12 Changes to Figure 5 ........................................................................ 12 Deleted Figure 6 Renumbered Sequentially .............................. 12 Updated Outline Dimensions ....................................................... 26 Change to Table 14 ........................................................................ 19 Changes to Ordering Guide .......................................................... 26 Updated Outline Dimensions ...................................................... 26 Changes to Ordering Guide .......................................................... 26 10/2017Rev. A to Rev. B Changed CP-32-7 to CP-32-2 ...................................... Throughout 9/2005Revision 0: Initial Version Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 Rev. C Page 2 of 28