1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9514 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.6 GHz differential clock input RSET VS GND 3 programmable dividers AD9514 LVPECL Divide-by in range from1 to 32 OUT0 Phase select for coarse delay adjust /1 . /32 OUT0B 2 independent 1.6 GHz LVPECL clock outputs Additive broadband output jitter 225 fs rms LVPECL 1 independent 800 MHz/250 MHz LVDS/CMOS clock output CLK OUT1 /1 . /32 Additive broadband output jitter 300 fs rms/290 fs rms CLKB OUT1B Time delays up to 10 ns LVDS/CMOS Device configured with 4-level logic pins OUT2 Space-saving, 32-lead LFCSP /1 . /32 t SYNCB OUT2B APPLICATIONS Low jitter, low phase noise clock distribution SETUP LOGIC Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 High performance instrumentation Figure 1. Broadband infrastructure ATE GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a The LVDS/CMOS output features a delay element with three design that emphasizes low jitter and phase noise to maximize selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each data converter performance. Other applications with with 16 steps of fine adjustment. demanding phase noise and jitter requirements also benefit from The AD9514 does not require an external controller for this part. operation or setup. The device is programmed by means of There are three independent clock outputs. Two of the outputs 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to V are LVPECL, and the third output can be set to either LVDS or S. The VREF pin provides a level of CMOS levels. The LVPECL outputs operate to 1.6 GHz, and VS. VS (3.3 V) and GND (0 V) provide the other two logic levels. the third output operates to 800 MHz in LVDS mode and to The AD9514 is ideally suited for data converter clocking 250 MHz in CMOS mode. applications where maximum converter performance is Each output has a programmable divider that can be set to achieved by encode signals with subpicosecond jitter. divide by a selected set of integers ranging from 1 to 32. The The AD9514 is available in a 32-lead LFCSP and operates from phase of one clock output relative to another clock output can a single 3.3 V supply. The temperature range is 40C to be set by means of a divider phase select function that serves as +85C. a coarse timing adjustment. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 20052020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. 05596-001AD9514 TABLE OF CONTENTS Features .............................................................................................. 1 Power-On SYNC .................................................................... 18 Applications ...................................................................................... 1 SYNCB ..................................................................................... 18 Functional Block Diagram .............................................................. 1 RSET Resistor ................................................................................ 19 General Description ......................................................................... 1 VREF ............................................................................................ 19 Revision History ............................................................................... 2 Setup Configuration .................................................................. 19 Specifications .................................................................................... 3 Divider Phase Offset .................................................................. 22 Clock Input ................................................................................... 3 Delay Block ................................................................................. 22 Clock Outputs ............................................................................... 3 Outputs ........................................................................................ 23 Timing Characteristics ................................................................ 4 Power Supply .............................................................................. 23 Clock Output Phase Noise .......................................................... 5 Exposed Metal Paddle ........................................................... 24 Clock Output Additive Time Jitter ............................................ 8 Power Management ................................................................... 24 SYNCB, VREF, and Setup Pins ................................................ 10 Applications .................................................................................... 25 Power ........................................................................................... 10 Using the AD9514 Outputs for ADC Clock Applications ... 25 Timing Diagrams ............................................................................ 11 LVPECL Clock Distribution ..................................................... 25 Absolute Maximum Ratings ......................................................... 12 LVDS Clock Distribution.......................................................... 26 Thermal Characteristics ............................................................ 12 CMOS Clock Distribution ........................................................ 26 ESD Caution................................................................................ 12 Setup Pins (S0 to S10) ................................................................ 26 Pin Configuration and Function Descriptions .......................... 13 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 26 Terminology .................................................................................... 14 Phase Noise and Jitter Measurement Setups .......................... 27 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 28 Functional Description .................................................................. 18 Ordering Guide .......................................................................... 28 Overall .......................................................................................... 18 CLK, CLKBDifferential Clock Input ................................... 18 Synchronizatio n .......................................................................... 18 REVISION HISTORY 11/2020Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Figure 6 ........................................................................ 13 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 7/2005Revision 0: Initial Version Rev. A Page 2 of 28