Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet AD9553 FEATURES GENERAL DESCRIPTION Input frequencies from 8 kHz to 710 MHz The AD9553 is a phase-locked loop (PLL) based clock translator Output frequencies up to 810 MHz LVPECL and LVDS (up to designed to address the needs of passive optical networks (PON) 200 MHz for CMOS output) and base stations. The device employs an integer-N PLL to Preset pin-programmable frequency translation ratios cover accommodate the applicable frequency translation requirements. popular wireline and wireless frequency applications, The user supplies up to two single-ended input reference signals or including xDSL, T1/E1, BITS, SONET, and Ethernet one differential input reference signal via the REFA and REFB Arbitrary frequency translation ratios via SPI port inputs. The device supports holdover applications by allowing the On-chip VCO user to connect a 25 MHz crystal resonator to the XTAL input. Accepts a crystal resonator for holdover applications The AD9553 is pin programmable, providing a matrix of standard Two single-ended (or one differential) reference input(s) input/output frequency translations from a list of 15 possible input Two output clocks (independently programmable as LVDS, frequencies to a list of 52 possible output frequency pairs (OUT1 LVPECL, or CMOS) and OUT2). The device also has a 3-wire SPI interface, enabling SPI-compatible, 3-wire programming interface the user to program custom input-to-output frequency translations. Single supply (3.3 V) The AD9553 output drivers are compatible with LVPECL, LVDS, Very low power: <450 mW (under most conditions) or single-ended CMOS logic levels, although the AD9553 is Small package size (5 mm 5 mm) implemented in a strictly CMOS process. Exceeds Telcordia GR-253-CORE jitter generation, transfer, and tolerance specifications The AD9553 operates over the extended industrial temperature range of 40C to +85C. APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON Wireless infrastructure Test and measurement (including handheld devices) BASIC BLOCK DIAGRAM AD9553 REFA INPUT FREQUENCY OUT2 OUTPUT PLL REFB SOURCE CIRCUITRY OUT1 SELECTOR XTAL PIN-DEFINED AND SERIAL PROGRAMMING Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2010 Analog Devices, Inc. All rights reserved. 08565-001AD9553 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Overview ..................................................................................... 16 General Description ......................................................................... 1 Preset Frequencies ...................................................................... 16 Basic Block Diagram ........................................................................ 1 Device Control Modes ............................................................... 19 Revision History ............................................................................... 2 Description of Functional Blocks ............................................. 20 Specifications ..................................................................................... 3 Jitter Tolerance ............................................................................ 26 Power Consumption .................................................................... 3 Output/Input Frequency Relationship .................................... 26 Logic Input Pins ............................................................................ 3 Calculating Divider Values ....................................................... 27 Logic Output Pins ......................................................................... 3 Low Dropout (LDO) Regulators .............................................. 28 RESET Pin ..................................................................................... 4 Automatic Power-On Reset ...................................................... 28 Applications Information .............................................................. 29 Reference Clock Input Characteristics ...................................... 4 Thermal Performance ................................................................ 29 VCO Characteristics .................................................................... 5 Serial Control Port ......................................................................... 30 Crystal Input Characteristics ...................................................... 5 Serial Control Port Pin Descriptions ....................................... 30 Output Characteristics ................................................................. 6 Operation of the Serial Control Port ....................................... 30 Jitter Characteristics ..................................................................... 7 Instruction Word (16 Bits) ........................................................ 31 Serial Control Port ....................................................................... 8 MSB/LSB First Transfers ........................................................... 31 Serial Control Port Timing ......................................................... 8 Register Map ................................................................................... 33 Absolute Maximum Ratings ............................................................ 9 Register Map Descriptions ........................................................ 35 ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 42 Pin Configuration and Function Descriptions ........................... 10 Ordering Guide .......................................................................... 42 Typical Performance Characteristics ........................................... 11 Input/Output Termination Recommendations .......................... 15 REVISION HISTORY 10/10Rev. 0 to Rev. A Changes to Table 16 ....................................................................... 19 Changes to Features Section, Applications Section, and General Changes to PLL (PFD, Charge Pump, VCO, Feedback Divider Description Section .......................................................................... 1 Section .............................................................................................. 22 Added Table Summary to Specifications Section ......................... 3 Changes to Loop Filter Section, Figure 31, Table 17, PLL Locked Added Supply Voltage Parameter, Table 1 ..................................... 3 Indicator Section, and Output Dividers Section ........................ 23 Changes to Table 5 ............................................................................ 4 Changes to Output Driver Mode Control Section ..................... 24 Changes to Table 6 and Crystal Load Capacitance Parameter, Changes to Output Driver Polarity (CMOS) Section ................ 25 Table 7 ................................................................................................ 5 Changes to Output/Input Frequency Relationship Section ...... 26 Changes to Table 8 ............................................................................ 6 Changes to Calculating Divider Values Section ......................... 27 Changes to Table 9 ............................................................................ 7 Changes to Automatic Power-On Reset Section ........................ 28 Changes to Pin 1 and Pin 15, Table 13 ......................................... 10 Changes to Thermal Performance Section ................................. 29 Added Figure 4, Renumbered Sequentially ................................ 11 Changes to Address 0x18, Address 0x32, and Address 0x34, Added Figure 10, Figure 12, Figure 13, and Figure 14............... 12 Table 27 ............................................................................................ 33 Added Input/Output Termination Recommendations Section, Changes to Address 0x18, Table 31 .............................................. 37 Change to Address 0x20, Table 34 ............................................... 38 Figure 25, Figure 26, and Figure 27 .............................................. 15 Moved Theory of Operation and Figure 28 ................................ 16 Changes to Address 0x24, Table 35 and Address 0x28, Table 36 ... 39 Changed General Description Section to Overview Section and Changes to Address 0x32, Table 37 .............................................. 40 Moved ............................................................................................... 16 Changes to Address 0x34, Table 39 .............................................. 41 Changes to Overview Section ....................................................... 16 4/10Revision 0: Initial Version Changes to Preset Frequencies Section and Table 14 ................ 17 Changes to Table 15 ........................................................................ 18 Rev. A Page 2 of 44