Fiber Channel/Ethernet Clock Generator IC, 7 Clock Outputs AD9572 FEATURES FUNCTIONAL BLOCK DIAGRAM REFSEL Fully integrated dual VCO/PLL cores 0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz XTAL CMOS 0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz OSC 1 25MHz 0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz REFCLK LDO Input crystal or clock frequency of 25 MHz LVPECL OR LVDS Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, VCO 100 MHz, and 125 MHz 2 106.25MHz Choice of LVPECL or LVDS output format Integrated loop filters LVPECL OR LVDS Copy of reference clock output 1 156.25MHz Rates configured via strapping pins LDO LVPECL 0.71 W power dissipation (LVDS operation) OR LVDS 1.07 W power dissipation (LVPECL operation) VCO 2 100MHz 3.3 V operation OR 125MHz Space saving, 6 mm 6 mm, 40-lead LFCSP CMOS 1 33.33MHz APPLICATIONS FORCE LOW Fiber channel line cards, switches, and routers AD9572 Gigabit Ethernet/PCIe support included FREQSEL Low jitter, low phase noise clock generation Figure 1. feedback divider and output divider. By connecting an external GENERAL DESCRIPTION crystal or reference clock to the REFCLK pin, frequencies up to The AD9572 provides a multioutput clock generator function 156.25 MHz can be locked to the input reference. Each output along with two on-chip PLL cores, optimized for fiber channel divider and feedback divider ratio is preprogrammed for the line card applications that include an Ethernet interface. The required output rates. integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency A second PLL also operates as an integer-N synthesizer and synthesizers to maximize network performance. Other applica- drives two LVPECL or LVDS output buffers for 106.25 MHz tions with demanding phase noise and jitter requirements also operation. No external loop filter components are required, thus benefit from this part. conserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm 6 mm lead frame The PLL section consists of a low noise phase frequency chip scale package (LFCSP) and can be operated from a single detector (PFD), a precision charge pump (CP), a low phase 3.3 V supply. The temperature range is 40C to +85C. noise voltage controlled oscillator (VCO), and a preprogrammed CPU 10G SFP+ ISLAND 1 156.25MHz 2 106.25MHz 16-PORT FIBRE CHANNEL ASIC 1 100MHz/125MHz AD9572 1 25MHz 1 33.33MHz QUAD SFP QUAD SFP QUAD SFP QUAD SFP PHY PHY PHY PHY Figure 2. Typical Application Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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PFD/CP PFD/CP LPF LPF THIRD 3RD ORDER ORDER 07498-002 DIVIDERS DIVIDERS 07498-001AD9572 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................9 Applications....................................................................................... 1 Pin Configuration and Function Descriptions........................... 10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 13 General Description ......................................................................... 1 Terminology.................................................................................... 15 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 16 Specifications..................................................................................... 3 Outputs ........................................................................................ 16 PLL Characteristics ...................................................................... 3 Phase Frequency Detector (PFD) and Charge Pump............ 17 LVDS Clock Output Jitter............................................................ 4 Power Supply............................................................................... 17 LVPECL Clock Output Jitter....................................................... 5 CMOS Clock Distribution ........................................................ 17 CMOS Clock Output Jitter.......................................................... 5 LVPECL Clock Distribution ..................................................... 18 Reference Input............................................................................. 5 LVDS Clock Distribution.......................................................... 18 Clock Outputs............................................................................... 6 Reference Input........................................................................... 18 Timing Characteristics ................................................................ 6 Power and Grounding Considerations and Power Supply Rejection...................................................................................... 19 Control Pins .................................................................................. 7 Outline Dimensions....................................................................... 20 Power.............................................................................................. 7 Ordering Guide .......................................................................... 20 Crystal Oscillator.......................................................................... 7 Timing Diagrams.............................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 REVISION HISTORY /11Rev. A to Rev. B Renumbered Figures Sequentially............................... Throughout Changes to Output Rise Time, tRC2 Parameter and Output Fall Changes to CMOS Clock Distribution Section.......................... 17 Time, t Parameter in Table 7....................................................... 6 Changes to LVPECL Clock Distribution Section, Added FC2 Figure 23 and Figure 24 ................................................................. 18 11/10Rev. 0 to Rev. A Changes to LVDS Clock Distribution Section, Added Changes to Features.......................................................................... 1 Figure 26 .......................................................................................... 18 Changes to Table 2............................................................................ 4 Changes to Reference Input Section ............................................ 18 Changes to Table 3 and Table 4....................................................... 5 Changes to Power and Grounding Considerations and Power Changes to Table 7............................................................................ 6 Supply Rejection Section ............................................................... 19 Added Figure 7 and Figure 8......................................................... 11 Added Figure 14, Figure 15, and Figure 16 ................................. 13 7/09Revision 0: Initial Version Deleted Original Figure 16 and Figure 19................................... 16 Rev. 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