11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet AD9737A/AD9739A FEATURES FUNCTIONAL BLOCK DIAGRAM Direct RF synthesis at 2.5 GSPS update rate RESET IRQ DC to 1.25 GHz in baseband mode AD9737A/AD9739A 1.25 GHz to 3.0 GHz in mix-mode SDIO 1.2V Industry leading single/multicarrier IF or RF synthesis SDO Dual-port LVDS data interface SPI CS DAC BIAS SCLK Up to 1.25 GSPS operation VREF Source synchronous DDR clocking I120 Pin compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS IOUTN TxDAC APPLICATIONS DCI CORE IOUTP Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics CLK DISTRIBUTION DLL (DIV-BY-4) DCO (MU CONTROLLER) DACCLK Figure 1. GENERAL DESCRIPTION The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high The AD9737A/AD9739A are manufactured on a 0.18 m performance RF DACs that are capable of synthesizing wideband CMOS process and operate from 1.8 V and 3.3 V supplies. signals from dc up to 3 GHz. The AD9737A/AD9739A are pin They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics. and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support PRODUCT HIGHLIGHTS synchronization or RZ mode, and are specified to operate 1. Ability to synthesize high quality wideband signals with between 1.6 GSPS and 2.5 GSPS. bandwidths of up to 1.25 GHz in the first or second By elimination of the synchronization circuitry, some nonideal Nyquist zone. artifacts such as images and discrete clock spurs remain stationary 2. A proprietary quad-switch DAC architecture provides on the AD9737A/AD9739A between power-up cycles, thus exceptional ac linearity performance while enabling mix- allowing for possible system calibration. AC linearity and noise mode operation. performance remain the same between the AD9739 and the 3. A dual-port, double data rate, LVDS interface supports the AD9737A/AD9739A. maximum conversion rate of 2500 MSPS. The inclusion of on-chip controllers simplifies system integration. 4. On-chip controllers manage external and internal clock A dual-port, source synchronous, LVDS interface simplifies the domain skews. digital interface with existing FGPA/ASIC technology. On-chip 5. Programmable differential current output with an 8.66 mA controllers are used to manage external and internal clock domain to 31.66 mA range. variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DB1 13:0 DB0 13:0 DATA CONTROLLER LVDS DDR LVDS DDR RECEIVER RECEIVER 4-TO-1 DATA ASSEMBLER DATA LATCH 09616-001AD9737A/AD9739A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map Description .................................................. 40 Applications ....................................................................................... 1 SPI Operation ............................................................................. 40 Functional Block Diagram .............................................................. 1 SPI Register Map ............................................................................ 42 General Description ......................................................................... 1 SPI Port Configuration and Software Reset ........................... 43 Product Highlights ........................................................................... 1 Power-Down LVDS Interface and TxDAC............................ 43 Revision History ............................................................................... 3 Controller Clock Disable ........................................................... 43 Specifications ..................................................................................... 4 Interrupt Request (IRQ) Enable/Status ................................... 44 DC Specifications ......................................................................... 4 TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 44 LVDS Digital Specifications ........................................................ 5 TxDAC Quad-Switch Mode of Operation .............................. 44 Serial Port Specifications ............................................................. 6 DCI Phase Alignment Status .................................................... 44 AC Specifications .......................................................................... 7 Data Receiver Controller Configuration ................................. 44 Absolute Maximum Ratings ............................................................ 8 Data Receiver Controller Data Sample Delay Value ............ 45 Thermal Resistance ...................................................................... 8 Data Receiver Controller DCI Delay Value/Window and Phase Rotation ............................................................................ 45 ESD Caution .................................................................................. 8 Data Receiver Controller Delay Line Status .......................... 45 Pin Configurations and Function Descriptions ........................... 9 Data Receiver Controller Lock/Tracking Status ..................... 45 Typical Performance CharacteristicsAD9737A...................... 14 CLK Input Common Mode ...................................................... 46 Static Linearity ............................................................................ 14 Mu Controller Configuration and Status ................................ 46 AC (Normal Mode) .................................................................... 15 Part ID.......................................................................................... 47 AC (Mix-Mode) .......................................................................... 17 Theory of Operation ...................................................................... 48 One-Carrier DOCSIS Performance (Normal Mode) ............ 20 LVDS Data Port Interface .......................................................... 49 Four-Carrier DOCSIS Performance (Normal Mode) ........... 21 Mu Controller ............................................................................. 52 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22 Interrupt Requests ...................................................................... 54 16-Carrier DOCSIS Performance (Normal Mode) ............... 23 Analog Interface Considerations .................................................. 55 32-Carrier DOCSIS Performance (Normal Mode) ............... 24 Analog Modes of Operation ..................................................... 55 64- and 128-Carrier DOCSIS Performance (Normal Mode)25 Clock Input Considerations ...................................................... 56 Typical Performance CharacteristicsAD9739A...................... 26 Voltage Reference ....................................................................... 57 Static Linearity ............................................................................ 26 Analog Outputs .......................................................................... 57 AC (Normal Mode) .................................................................... 28 Output Stage Configuration ..................................................... 59 AC (Mix-Mode) .......................................................................... 31 Nonideal Spectral Artifacts ....................................................... 60 One-Carrier DOCSIS Performance (Normal Mode) ............ 33 Lab Evaluation of the AD9737A/AD9739A ........................... 61 Four-Carrier DOCSIS Performance (Normal Mode) ........... 34 Recommended Start-Up Sequence .......................................... 61 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35 Outline Dimensions ....................................................................... 63 16-Carrier DOCSIS Performance (Normal Mode) ............... 36 Ordering Guide .......................................................................... 63 32-Carrier DOCSIS Performance (Normal Mode) ............... 37 64- and 128-Carrier DOCSIS Performance (Normal Mode)38 Terminology .................................................................................... 39 Serial Port Interface (SPI) Register............................................... 40 Rev. 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