IF Digitizing Subsystem Data Sheet AD9864 FEATURES GENERAL DESCRIPTION 1 10 MHz to 300 MHz input frequency The AD9864 is a general-purpose IF subsystem that digitizes a 6.8 kHz to 270 kHz output signal bandwidth low level, 10 MHz to 300 MHz IF input with a signal bandwidth 7.5 dB single sideband noise figure (SSB NF) ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 7.0 dBm input third-order intercept (IIP3) consists of a low noise amplifier (LNA), a mixer, a band-pass - AGC free range up to 34 dBm analog-to-digital converter (ADC), and a decimation filter with 12 dB continuous AGC range programmable decimation factor. An automatic gain control 16 dB front -end attenuator (AGC) circuit gives the AD9864 12 dB of continuous gain Baseband I/Q 16-bit (or 24-bit) serial digital output adjustment. Auxiliary blocks include both clock and local LO and sampling clock synthesizers oscillator (LO) synthesizers. Programmable decimation factor, output format, AGC, and The high dynamic range of the AD9864 and inherent antialiasing synthesizer settings provided by the band-pass - c onverter allow the device to cope 370 input impedance with blocking signals up to 95 dB stronger than the desired signal. 2.7 V to 3.6 V supply voltage This attribute often reduces the cost of a radio by reducing IF Low current consumption: 17 mA filtering requirements. Also, it enables multimode radios of varying 48-lead LFCSP package channel bandwidths, allowing the IF filter to be specified for the APPLICATIONS largest channel bandwidth. Multimode narrow-band radio products The SPI port programs numerous parameters of the AD9864, Analog/digital UHF/VHF FDMA receivers allowing the device to be optimized for any given application. TETRA, APCO25, GSM/EDGE Programmable parameters include synthesizer divide ratios, AGC Portable and mobile radio products attenuation and attack/decay time, received signal strength level, SATCOM terminals decimation factor, output data format, 16 dB attenuator, and the selected bias currents. The AD9864 is available in a 48-lead LFCSP package and operates from a single 2.7 V to 3.6 V supply. The total power consumption is typically 56 mW and a power-down mode is provided via serial interfacing. FUNCTIONAL BLOCK DIAGRAM MXOP MXON IF2P IF2N GCP GCN DAC AGC AD9864 16dB DECIMATION LNA - ADC FORMATTING/SSI DOUTA IFIN FILTER DOUTB FS CLKOUT FREF CONTROL LOGIC LO VOLTAGE CLK SYN SYN REFERENCE SPI IOUTL LOP LON IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB LO VCO AND LOOP FILTER LOOP FILTER Figure 1. 1 Protected by U.S. Patent No. 5,969,657 other patents pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 04319-0-001AD9864 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SSI Control Registers ................................................................. 21 Applications ....................................................................................... 1 Synchronization Using SYNCB ................................................ 24 General Description ......................................................................... 1 Interfacing to DSPs .................................................................... 24 Functional Block Diagram .............................................................. 1 Power Control ............................................................................. 24 Revision History ............................................................................... 2 LO Synthesizer ............................................................................ 25 Specif icat ions ..................................................................................... 3 Clock Synthesizer ....................................................................... 26 Digital Specifications ................................................................... 5 IF LNA/Mixer ............................................................................. 28 Absolute Maximum Ratings ............................................................ 6 Band-Pass - ADC .................................................................. 29 Thermal Resistance ...................................................................... 6 Decimation Filter ....................................................................... 32 ESD Caution .................................................................................. 6 Variable Gain Amplifier Operation with Automatic Gain Control ............................................................................... 33 Pin Configuration and Functional Descriptions .......................... 7 Applications Considerations ..................................................... 38 Typical Performance Characteristics ............................................. 9 External Passive Component Requirements .......................... 40 Terminology .................................................................................... 14 Applications ................................................................................ 40 Serial Peripheral Interface (SPI) ................................................... 15 Layout Example, Evaluation Board, and Software ................. 45 Theory of Operation ...................................................................... 17 SPI Initialization Example ......................................................... 45 Introduction ................................................................................ 17 Device SPI Initialization ............................................................ 46 Serial Port Interface (SPI) .......................................................... 18 Outline Dimensions ....................................................................... 47 Power-On Reset .......................................................................... 19 Ordering Guide .......................................................................... 47 Synchronous Serial Interface (SSI) ........................................... 19 REVISION HISTORY 2/16Rev. 0 to Rev. A Changes to Band-Pass - ADC Section and Table 20 ............ 30 Changes to Figure 2 .......................................................................... 7 Changes to Table 21 ....................................................................... 31 Changes to Typical Performance Characteristics Section ........... 9 Changes to Variable Gain Control Section ................................. 34 Changes to Figure 19 ...................................................................... 11 Deleted Table 17 ............................................................................. 34 Changes to Table 6 .......................................................................... 16 Added Figure 64 ............................................................................. 36 Changed General Description Section to Introduction Section ... 17 Changes to Figure 72...................................................................... 40 Changes to Serial Port Interface (SPI) Section ........................... 18 Changes to Layout Example, Evaluation Board, and Added Figure 31 Renumbered Sequentially .............................. 19 Software Section ............................................................................. 45 Added Power-On Reset Section ................................................... 19 Added Figure 77 and SPI Initialization Example Section ......... 45 Deleted Table 9 Renumbered Sequentially ................................ 19 Added Device SPI Initialization Section and Table 24 .............. 46 Added SSI Control Registers Section and Table 8 to Table 13 .... 21 Updated Outline Dimensions ....................................................... 47 Changes to Synchronization Using SYNCB Section and Changes to Ordering Guide .......................................................... 47 Figure 38 .......................................................................................... 24 Changes to Clock Synthesizer Section ......................................... 26 8/03Revision 0: Initial Version Rev. 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