Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF4372 FEATURES GENERAL DESCRIPTION RF output frequency range: 62.5 MHz to 16,000 MHz The ADF4372 allows implementation of fractional-N or integer-N Fractional-N synthesizer and integer-N synthesizer phase-locked loop (PLL) frequency synthesizers when used with High resolution 39-bit fractional modulus an external loop filter and an external reference frequency. The Typical spurious f : 90 dBc PFD wideband microwave voltage controlled oscillator (VCO) design Integrated rms jitter: 38 fs (1 kHz to 100 MHz) allows frequencies from 62.5 MHz to 16 GHz to be generated. Normalized phase noise floor: 234 dBc/Hz The ADF4372 has an integrated VCO with a fundamental output f operation to 250 MHz PFD frequency ranging from 4000 MHz to 8000 MHz. In addition, the Reference input frequency operation to 600 MHz VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64 Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output circuit that allows the user to generate radio frequency (RF) 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x output frequencies as low as 62.5 MHz at RF8x. A frequency 8,000 MHz to 16,000 MHz output at RF16x multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x Lock time approximately 3 ms with automatic calibration duplicates the frequency range of RF8x or permits direct access to Lock time <30 s with autocalibration bypassed, typical the VCO output. To suppress the unwanted products of frequency Analog and digital power supplies: 3.3 V typical multiplication, a harmonic filter exists between the multiplier and VCO supply voltage: 3.3 V and 5 V the output stage of RF16x. RF output mute function Control of all on-chip registers is through a 3-wire interface. 7 mm 7 mm, 48-terminal LGA package The ADF4372 operates with analog and digital power supplies APPLICATIONS ranging from 3.15 V to 3.45 V, and 5 V for the VCO power Wireless infrastructure (multicarrier global system for supply. The ADF4372 also contains hardware and software mobile communication (MC-GSM), 5G) power-down modes. Test equipment and instrumentation Clock generation Aerospace and defense FUNCTIONAL BLOCK DIAGRAM VCC CAL VCC VCO VCC LDO VCC X1 VCC X2 VCC MUX VCC 3V VDD NDIV VDD LS VCC LDO 3V VCC REF VDD PFD VDD VP MUX MUXOUT 5-BIT R 2 REFP 2 COUNTER DIVIDER DOUBLER RS SW REFN LOCK DETECT VCC REG OUT ADF4372 SCLK CHARGE SDIO DATA REGISTER CPOUT FUNCTION PUMP LATCH CS VTUNE PHASE COMPARATOR TRACKING 8GHz FILTER TO 16GHz VCO RF16P OUTPUT LOW 2 CORE STAGE RF16N NOISE LDO INTEGER FRACTION MODULUS 62.5MHz TO 8000MHz REGISTER REGISTER REGISTER 1, 2, 4, 8, RF8P OUTPUT 16, 32, 64 STAGE RF8N THIRD-ORDER FRACTIONAL INTERPOLATOR MUX 62.5MHz TO 8000MHz N COUNTER RFAUX8P OUTPUT MUX STAGE RFAUX8N GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20192021 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 16984-001ADF4372 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PFD and Charge Pump .............................................................. 19 Applications ....................................................................................... 1 MUXOUT and Lock Detect ...................................................... 19 General Description ......................................................................... 1 Double Buffers ............................................................................ 19 Functional Block Diagram .............................................................. 1 VCO ............................................................................................. 20 Revision History ............................................................................... 2 VCO ALC Threshold ................................................................. 20 Specifications ..................................................................................... 3 Output Stage ................................................................................ 20 Timing Specifications .................................................................. 7 Doubler ........................................................................................ 21 Absolute Maximum Ratings ............................................................ 8 Phase Adjust and Spur Optimization by Using PHASE WORD .......................................................................... 21 Thermal Resistance ...................................................................... 8 SPI ................................................................................................. 21 Electrostatic Discharge (ESD) Ratings ...................................... 8 Device Setup .................................................................................... 23 ESD Caution .................................................................................. 8 Step 1: Set Up the SPI Interface ................................................ 23 Pin Configuration and Function Descriptions ............................. 9 Step 2: Initialization Sequence .................................................. 23 Typical Performance Characteristics ........................................... 11 Step 3: Frequency Update Sequence ........................................ 23 Theory of Operation ...................................................................... 15 Applications Information .............................................................. 24 RF Synthesizer, a Worked Example .......................................... 15 Power Supplies ............................................................................ 24 Reference Input Sensitivity ........................................................ 15 PCB Design Guidelines for an LGA Package ......................... 24 Reference Doubler and Reference Divider ............................. 16 Output Matching ........................................................................ 24 Spurious Optimization and Fast Lock ..................................... 16 Register Summary .......................................................................... 25 Optimizing Jitter ......................................................................... 16 Register Details ............................................................................... 27 Spur Mechanisms ....................................................................... 16 Outline Dimensions ....................................................................... 48 Lock Time .................................................................................... 16 Ordering Guide .......................................................................... 48 Circuit Description ......................................................................... 18 Reference Input ........................................................................... 18 RF N Divider ............................................................................... 18 REVISION HISTORY 9/2021Rev. 0 to Rev. A Changes to Address: 0x23, Default: 0x00, Name: REG0023 Changes to Table 1 ............................................................................ 3 Section and Table 33 ...................................................................... 34 Changes to Table 3 and Table 4 ....................................................... 8 Changes to Address: 0x25, Default: 0x07, Name: REG0025 Added Electrostatic Discharge (ESD) Ratings Section and Section and Table 35 ...................................................................... 35 Table 5 Renumbered Sequentially ................................................. 8 Changes to Address: 0x2A, Default: 0x00, Name: REG002A Changes to Table 6 ............................................................................ 9 Section and Table 39 ...................................................................... 37 Changes to Figure 29 and INT, FRAC, MOD, and R Counter Changes to Table 40 ....................................................................... 38 Relationship Section ....................................................................... 18 Changed Address: 0x2E, Default: 0x12, Name: REG002E Added Phase Adjust and Spur Optimization by Using Section to Address: 0x2E, Default: 0x10, Name: REG002E PHASE WORD Section ................................................................ 21 Section .............................................................................................. 39 Deleted Output Stage Mute Section ............................................. 22 Changes to Table 42, Address: 0x2E, Default: 0x10, Name: Added VCO ALC Threshold Section........................................... 20 REG002E Section, and Table 43 ................................................... 39 Changes to Output Stage Section ................................................. 20 Changed Address: 0x2F, Default: 0x94, Name: REG002F Section Changes to Step 3: Frequency Update Sequence Section .......... 22 to Address: 0x2F, Default: 0x92, Name: REG002F Section ....... 40 Changes to Table 9 .......................................................................... 25 Changes to Table 44 ....................................................................... 40 Changes to Table 26, Table 27, and Table 28 ............................... 31 Changes to Table 50 ....................................................................... 42 Changes to Table 29 ........................................................................ 32 Changes to Table 54 ....................................................................... 43 Changes to Table 30 and Table 31 ................................................ 33 8/2019Revision 0: Initial Version Rev. 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