120 dB Range (3 nA to 3 mA) Dual Logarithmic Converter Data Sheet ADL5310 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 independent channels optimized for photodiode interfacing 665k VREF VRDZ OUT1 VSUM 6-decade input dynamic range V OUT1 COMM Law conformance 0.3 dB from 3 nA to 3 mA Temperature-stable logarithmic outputs IRF1 Nominal slope 10 mV/dB (200 mV/dec), externally scalable SCL1 V BIAS BIN1 6.69k Intercepts may be independently set by external resistors I User-configurable output buffer amplifiers LOG TEMPERATURE VNEG COMPENSATION 451 LOG1 Single-supply or dual-supply operation 14.2k Space efficient, 24-lead 4 mm 4 mm LFCSP I INP1 PD1 Low power: <10 mA quiescent current OUT2 REFERENCE 0.5V 2.5V V GENERATOR OUT2 APPLICATIONS 20k 80k COMM Gain and absorbance measurements IRF2 Multichannel power monitoring SCL2 V BIAS 14.2k BIN2 General-purpose baseband log compression I LOG TEMPERATURE VNEG COMPENSATION 451 LOG2 6.69k I INP2 PD2 COMM VSUM 665k VREF Figure 1. GENERAL DESCRIPTION 1 VSUM potential. The VSUM potential is internally set to 500 mV The ADL5310 low cost, dual logarithmic amplifier converts input but may be externally grounded for dual-supply operation, and current over a wide dynamic range to a linear-in-dB output for additional applications requiring voltage inputs. voltage. It is optimized to determine the optical power in wide- ranging optical communication system applications, including The logarithmic slope is set to 10 mV/dB (200 mV/decade) control circuitry for lasers, optical switches, atten-uators, and nominal and can be modified using external resistors and the amplifiers, as well as system monitoring. The device is equivalent independent buffer amplifiers. The logarithmic intercepts for to a dual AD8305 with enhanced dynamic range (120 dB). While each channel are defined by the individual reference currents, the ADL5310 contains two independent signal channels with which are set to 3 A nominal for maximum input range by individually configurable transfer function constants (slope and connecting 665 k resistors between the 2.5 V VREF pins and intercept), internal bias circuitry is shared between channels for the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets improved power consumption and channel matching. Dual the x-intercept four decades below the reference current, which converters in a single, compact LFCSP package yield space- is typically 300 pA for a 3 A reference. efficient solutions for measuring gain or attenuation across The use of individually optimized reference currents may be optical elements. Only a single supply is required optional valuable when using the ADL5310 for gain or absorbance measure- dual-supply operation offers added flexibility. ments where each channel input has a different current range The ADL5310 employs an optimized translinear structure that requirement. The reference current inputs are also fully functional use the accurate logarithmic relationship between a bipolar dynamic inputs, allowing log ratio operation with the reference transistors base emitter voltage and collector current, with input current as the denominator. The ADL5310 is specified for appropriate scaling by precision currents to compensate for the operation from 40C to +85C. inherent temperature dependence. Input and reference current pins sink current ranging from 3 nA to 3 mA (limited to 60 dB 1 Protected by US Patents 4,604,532, and 5,519,308. Other patents pending. between input and reference) into a fixed voltage defined by the Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 4.99k 4.99k 04415-0-001ADL5310 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory .......................................................................................... 11 Applications ....................................................................................... 1 Managing Intercept and Slope .................................................. 12 Functional Block Diagram .............................................................. 1 Response Time and Noise Considerations ............................. 12 General Description ......................................................................... 1 Applications Information .............................................................. 13 Revision History ............................................................................... 2 Calibration ................................................................................... 14 Specifications ..................................................................................... 3 Minimizing Crosstalk ................................................................ 14 Absolute Maximum Ratings ............................................................ 4 Relative and Absolute Power Measurements .......................... 15 ESD Caution .................................................................................. 4 Characterization Methods ........................................................ 16 Pin Configuration and Function Descriptions ............................. 5 Evaluation Board ............................................................................ 17 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 20 General Structure ........................................................................... 11 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/2018Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 5 Changes to Figure 40 ...................................................................... 18 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 9/2004Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 20 11/2003Revision 0: Initial Version Rev. B Page 2 of 20