Dual, 200 mA, High Performance RF LDO with Load Switch ADP5030 FEATURES APPLICATIONS Input voltage range: 2.5 V to 5.5 V RF subsystems Dual, 200 mA low dropout voltage regulators GPS devices Tiny, 16-ball, 1.6 mm 1.6 mm WLCSP GENERAL DESCRIPTION Initial accuracy: 0.7% The ADP5030 combines two high performance, low dropout Stable with 1 F ceramic output capacitors (LDO) voltage regulators, a low RDS load switch, and level ON Overcurrent and thermal protection shifting logic in a tiny, 16-ball, 1.6 mm 1.6 mm WLCSP to High PSRR meet demanding performance and board space requirements. 76 dB up to 1 kHz 70 dB at 10 kHz The low quiescent current, low dropout voltage, and wide input 60 dB at 100 kHz voltage range of the ADP5030 LDOs extend the battery life of 40 dB at 1 MHz portable devices. The ADP5030 LDOs maintain power supply Low output noise rejection greater than 60 dB for frequencies as high as 100 kHz 27 V rms typical output noise at V = 1.2 V OUTx while operating with a low headroom voltage. 50 V rms typical output noise at V = 2.8 V OUTx The ADP5030 can be configured in two different activation Excellent transient response modes for LDO2 and the load switch these modes are selected Low dropout voltage: 175 mV at 200 mA load by a dedicated pin (MSEL). 60 A typical ground current at no load, both LDOs enabled Guaranteed 200 mA output current per regulator Load switch with low RDS of 100 m at 1.8 V ON High-to-low voltage and low-to-high voltage level shifting logic 40C to +125C junction temperature FUNCTIONAL BLOCK DIAGRAM POWER SUPPLY AND PERIPHERAL VIN3 VIN3 PROCESSOR ADP5030 MODULE VIN1 VOUT1 VDD LDO1 VBB C1 C2 EN1 1F 1F VOUT2 GPO4 1V8 LDO2 VAUX MSEL C3 1F V1 8DIG VIN2 VOUT3 LOAD VIO SWITCH C4 C5 0.1F 2.2F VIN2 EN2 GPO2 1V8 VIN3 GPOUT1 GPIN1 GPI0 1V8 GPO0 1V2 GPIN2 GPOUT2 GPO0 1V8 GPI0 1V2 VIN3 GPIN3 GPOUT3 GPO1 1V8 GPI1 1V2 1.8V INPUT/OUTPUT GND 1.2V INPUT/OUTPUT SYSTEM SYSTEM Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07893-001ADP5030 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Applications Information .............................................................. 14 General Description ......................................................................... 1 LDO2 and Load Switch Activation Logic ............................... 15 Functional Block Diagram .............................................................. 1 Sequencing .................................................................................. 15 Revision History ............................................................................... 2 Capacitor Selection .................................................................... 15 Specif icat ions ..................................................................................... 3 Undervoltage Lockout ............................................................... 16 Input and Output Capacitor, Recommended Specifications .. 4 Enable Feature ............................................................................ 16 Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Overload Protection ................. 17 Thermal Data ................................................................................ 5 Thermal Considerations ............................................................ 17 Thermal Resistance ...................................................................... 5 PCB Layout Considerations ...................................................... 19 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 20 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 20 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 11/09Rev. A to Rev. B Changes to Figure 36 and Figure 37 Captions ............................ 14 9/09Rev. 0 to Rev. A Changes to Output Noise Parameter Level Shifter, GPOUT1 Output Logic Low and GPOUT2, GPOUT3 Output Logic Low Parameters, Table 1 ........................................................................... 3 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Input and Output Capacitor Properties Section .... 15 6/09Revision 0: Initial Version Rev. B Page 2 of 2