20 V, 300 mA, Low Noise, CMOS LDO Data Sheet ADP7102 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 3.3 V to 20 V VOUT = 5V VIN = 8V VIN VOUT Maximum output current: 300 mA + + CIN COUT 1F 1F Low noise: 15 V rms for fixed output versions SENSE RPG PSRR performance of 60 dB at 10 kHz, V = 3.3 V OUT R1 ON 100k 100k EN/ OFF Reverse current protection UVLO R2 PG PG Low dropout voltage: 200 mV at 300 mA load 100k GND Initial accuracy: 0.8% Accuracy over line, load, and temperature: 2%, +1% Low quiescent current (V = 5 V), I = 750 A with 300 mA load IN GND Figure 1. ADP7102 with Fixed Output Voltage, 5 V Low shutdown current: 40 A at V = 12 V IN Stable with small 1 F ceramic output capacitor VIN VOUT VOUT = 5V VIN = 8V + + CIN R1 COUT 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 1F 40.2k 1F ADJ 5 V, and 9 V R2 R3 13k Adjustable output from 1.22 V to V V ON IN DO 100k RPG EN/ OFF 100k Foldback current limit and thermal overload protection UVLO R4 PG PG 100k User programmable precision UVLO/enable GND Power-good indicator 8-lead LFCSP and 8-lead SOIC packages Figure 2. ADP7102 with Adjustable Output Voltage, 5 V APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7102 is a CMOS, low dropout linear regulator that The ADP7102 output noise voltage is 15 V rms and is operates from 3.3 V to 20 V and provides up to 300 mA of output independent of the output voltage. A digital power-good output current. This high input voltage LDO is ideal for regulation of high allows power system monitors to check the health of the output performance analog and mixed signal circuits operating from voltage. A user programmable precision undervoltage lockout 19 V to 1.22 V rails. Using an advanced proprietary architecture, it function facilitates sequencing of multiple power supplies. provides high power supply rejection, low noise, and achieves The ADP7102 is available in 8-lead, 3 mm 3 mm LFCSP and excellent line and load transient response with just a small 1 F 8-lead SOIC packages. The LFCSP offers a very compact solution ceramic output capacitor. and also provides excellent thermal performance for applications The ADP7102 is available in seven fixed output voltage options requiring up to 300 mA of output current in a small, low profile and an adjustable version, which allows output voltages that footprint. range from 1.22 V to VIN VDO via an external feedback divider. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09506-002 09506-001ADP7102 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Applications Information .............................................................. 18 Typical Application Circuits ............................................................ 1 Capacitor Selection .................................................................... 18 General Description ......................................................................... 1 Programable Undervoltage Lockout (UVLO) ........................... 19 Revision History ............................................................................... 2 Power-Good Feature .................................................................. 20 Specif icat ions ..................................................................................... 3 Noise Reduction of the Adjustable ADP7102 ............................ 20 Input and Output Capacitor, Recommended Specifications .. 4 Current Limit and Thermal Overload Protection ................. 21 Absolute Maximum Ratings ............................................................ 5 Thermal Considerations ............................................................ 21 Thermal Data ................................................................................ 5 Printed Circuit Board Layout Considerations ............................ 24 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 25 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 9/15Rev. D to Rev. E Changes to Figure 60 ...................................................................... 17 5/14Rev. C to Rev. D Changed UVLO Threshold Rising Typ Parameter from 1.23 V to 1.22 V Table 1 ............................................................................... 4 Changes to Power Good Section .................................................. 20 Updated Outline Dimensions ....................................................... 26 8/13Rev. B to Rev. C Changes to Table 3 ............................................................................ 5 2/13Rev. A to Rev. B Changes to Noise Reduction of the Adjustable ADP7102 Section .............................................................................................. 20 11/11Rev. 0 to Rev. A Changes to Figure 50 ...................................................................... 14 10/11Revision 0: Initial Version Rev. E Page 2 of 28