Multiformat SDTV Video Decoder ADV7183B 0.5 V to 1.6 V analog signal input range FEATURES Differential gain: 0.5% typ Multiformat video decoder supports NTSC-(J, M, 4.43), Differential phase: 0.5 typ PAL-(B/D/G/H/I/M/N), SECAM Programmable video controls Integrates three 54 MHz, 10-bit ADCs Peak white/hue/brightness/saturation/contrast Clocked from a single 27 MHz crystal Integrated on-chip video timing generator Line-locked clock-compatible (LLC) Free-run mode (generates stable video output with no I/P) Adaptive Digital Line Length Tracking (ADLLT), signal VBI decode support for close captioning, WSS, CGMS, EDTV, processing, and enhanced FIFO management give mini- TBC functionality Gemstar 1/2 Power-down mode 5-line adaptive comb filters 2 2-wire serial MPU interface (I C-compatible) Proprietary architecture for locking to weak, noisy, and unstable video sources such as VCRs and tuners 3.3 V analog, 1.8 V digital core 3.3 V IO supply Subcarrier frequency lock and status information output 2 temperature grades: 0C to +70C and 40C to +85C Integrated AGC with adaptive peak white mode 80-lead LQFP Pb-free package Macrovision copy protection detection Chroma transient improvement (CTI) APPLICATIONS Digital noise reduction (DNR) DVD recorders Multiple programmable analog input formats Video projectors Composite video (CVBS) HDD-based PVRs/DVDRs S-Video (Y/C) LCD TVs YPrPb component (VESA, MII, SMPTE, and BetaCam) Set-top boxes 12 analog video input channels Security systems Automatic NTSC/PAL/SECAM identification Digital televisions Digital output formats (8-bit or 16-bit) AVR receivers ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD GENERAL DESCRIPTION combinations. AGC and clamp restore circuitry allow an input The ADV7183B integrated video decoder automatically detects video signal peak-to-peak range of 0.5 V up to 1.6 V. and converts a standard analog baseband television signal- Alternatively, these can be bypassed for manual settings. compatible with worldwide standards NTSC, PAL, and SECAM into 4:2:2 component video data-compatible with 16-/8-bit The fixed 54 MHz clocking of the ADCs and datapath for all CCIR601/CCIR656. modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data The advanced and highly flexible digital output interface rate, timing signals, and output clock signals to be synchronous, enables performance video decoding and conversion in line- asynchronous, or line locked even with 5% line length variation. locked clock-based systems. This makes the device ideally The output control signals allow glueless interface connections suited for a broad range of applications with diverse analog in almost any application. The ADV7183B modes are set up video characteristics, including tape-based sources, broadcast 2 over a 2-wire, serial, bidirectional port (I C-compatible). sources, security/surveillance cameras, and professional systems. The ADV7183B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality The 10-bit accurate A/D conversion provides professional with lower power dissipation. quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode. The ADV7183B is packaged in a small 80-lead LQFP Pb-free package. The 12 analog input channels accept standard composite, S-Video, YPrPb video signals in an extensive number of Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. ADV7183B TABLE OF CONTENTS Introduction ...................................................................................... 4 VBI Data Recovery..................................................................... 21 Analog Front End......................................................................... 4 General Setup.............................................................................. 21 Standard Definition Processor (SDP)........................................ 4 Color Controls............................................................................ 23 Functional Block Diagram .......................................................... 5 Clamp Operation........................................................................ 25 specifications ..................................................................................... 6 Luma Filter .................................................................................. 26 Electrical Characteristics............................................................. 6 Chroma Filter.............................................................................. 29 Video Specifications..................................................................... 7 Gain Operation........................................................................... 30 Timing Specifications .................................................................. 8 Chroma Transient Improvement (CTI) .................................. 33 Analog Specifications................................................................... 8 Digital Noise Reduction (DNR)............................................... 34 Thermal Specifications ................................................................ 9 Comb Filters................................................................................ 35 Timing Diagrams.......................................................................... 9 AV Code Insertion and Controls ............................................. 37 Absolute Maximum Ratings.......................................................... 10 Synchronization Output Signals............................................... 39 ESD Caution................................................................................ 10 Sync Processing .......................................................................... 46 Pin Configuration and Function Descriptions........................... 11 VBI Data Decode ....................................................................... 47 Analog Front End ........................................................................... 13 Pixel Port Configuration ............................................................... 59 Analog Input Muxing ................................................................ 13 MPU Port Description................................................................... 60 Manual Input Muxing................................................................ 15 Register Accesses........................................................................ 61 Global Control Registers ............................................................... 16 Register Programming............................................................... 61 2 Power-Save Modes...................................................................... 16 I C Sequencer.............................................................................. 61 Reset Control .............................................................................. 16 IP2PC Register Maps ..................................................................... 62 2P Global Pin Control ..................................................................... 17 I C Register Map Details ........................................................... 118H66 2 Global Status Registers................................................................... 19 52HI C Programming Examples.......................................................... 119H88 Identification............................................................................... 19 E53H xamples in this Section use a 28 MHz Clock..................... 88120H Status 1 ......................................................................................... 19 54HExamples Using 27 MHz Clock................................................ 92121H Autodetection Result.................................................................. 19 PCB L55H ayout Recommendations.................................................... 94122H Status 2 ......................................................................................... 19 56HAnalog Interface Inputs............................................................. 94123H Status 3 ......................................................................................... 19 57HPower Supply Decoupling ......................................................... 124H94 Standard Definition Processor (SDP).......................................... 20 P58H LL ............................................................................................... 94125H SD Luma Path ............................................................................. 20 59HDigital Outputs (Both Data and Clocks) ................................ 94126H SD Chroma Path......................................................................... 20 Dig60H ital Inputs .............................................................................. 94127H Sync Processing........................................................................... 21 61HAntialiasing Filters ..................................................................... 95128H Rev. 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