Multiformat SDTV Video Decoder ADV7189B FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), 0.5 V to 1.6 V analog signal input range PAL-(B/D/G/H/I/M/N), SECAM Differential gain: 0.4% typ Integrates three 54 MHz, Noise Shaped Video, 12-bit ADCs Differential phase: 0.4 typ Clocked from a single 28 MHz crystal Programmable video controls Line-locked clock-compatible (LLC) Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Adaptive-Digital-Line-Length-Tracking (ADLLT), signal processing, and enhanced FIFO management gives mini- Free-run mode (generates stable video output with no I/P) TBC functionality VBI decode support for close captioning, WSS, CGMS, EDTV, 5-line adaptive comb filters Gemstar 1/2 Proprietary architecture for locking to weak, noisy, and Power-down mode unstable video sources such as VCRs and tuners 2 2-wire serial MPU interface (I C-compatible) Subcarrier frequency lock and status information output 3.3 V analog, 1.8 V digital core 3.3 V IO supply Integrated AGC with adaptive peak white mode 2 temperature grades: 0C to +70C and 40C to +85C Macrovision copy protection detection 80-lead LQFP Pb-free package CTI (chroma transient improvement) DNR (digital noise reduction) APPLICATIONS Multiple programmable analog input formats High-end DVD recorders CVBS (composite video) Video projectors S-Video (Y/C) HDD-based PVRs/DVDRs YPrPb component (VESA, MII, SMPTE, and BetaCam) LCD TVs 12 analog video input channels Set-top boxes Automatic NTSC/PAL/SECAM identification Professional video products Digital output formats (8-bit/10-bit/16-bit/20-bit) AVR receivers ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD GENERAL DESCRIPTION The ADV7189B integrated video decoder automatically detects The 12 analog input channels accept standard composite, and converts a standard analog baseband television signal, com- S-Video, YPrPb video signals in an extensive number of patible with worldwide standards NTSC, PAL, and SECAM into combinations. AGC and clamp restore circuitry allow an 4:2:2 component video data-compatible with 20-, 16-, 10-, and input video signal peak-to-peak range of 0.5 V to 1.6 V. 8-bit CCIR601/CCIR656. Alternatively, these can be bypassed for manual settings. The advanced and highly flexible digital output interface The fixed 54 MHz clocking of the ADCs and datapath for enables performance video decoding and conversion in line- all modes allows very precise, accurate sampling and digital locked, clock-based systems. This makes the device ideally filtering. The line-locked clock output allows the output data suited for a broad range of applications with diverse analog rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional The output control signals allow glueless interface connections systems. in almost any application. The ADV7189B modes are set up 2 over a 2-wire, serial, bidirectional port (I C-compatible). The 12-bit accurate A/D conversion provides professional quality video performance and is unmatched. This allows The ADV7189B is fabricated in a 3.3 V CMOS process. Its true 10-bit resolution in the 10-bit output mode. monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7189B is packaged in a small, 80-lead LQFP Pb-free package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. ADV7189B TABLE OF CONTENTS Introduction ...................................................................................... 4 General Setup.............................................................................. 21 Analog Front End......................................................................... 4 SD Color Controls...................................................................... 23 Standard Definition Processor ................................................... 4 Clamp Operation........................................................................ 25 Functional Block Diagram .............................................................. 5 Luma Filter .................................................................................. 26 Specifications..................................................................................... 6 Chroma Filter.............................................................................. 29 Electrical Characteristics............................................................. 6 Gain Operation........................................................................... 30 Video Specifications..................................................................... 7 Chroma Transient Improvement (CTI) .................................. 34 Timing Specifications .................................................................. 8 Digital Noise Reduction (DNR)............................................... 34 Analog Specifications................................................................... 8 Comb Filters................................................................................ 35 Thermal Specifications ................................................................ 9 AV Code Insertion and Controls ............................................. 38 Timing Diagrams.......................................................................... 9 Synchronization Output Signals............................................... 40 Absolute Maximum Ratings.......................................................... 10 Sync Processing .......................................................................... 48 ESD Caution................................................................................ 10 VBI Data Decode ....................................................................... 48 Pin Configuration and Function Descriptions........................... 11 Pixel Port Configuration ............................................................... 60 Analog Front End ........................................................................... 13 MPU Port Description................................................................... 61 Analog Input Muxing ................................................................ 13 Register Accesses........................................................................ 62 Global Control Registers ............................................................... 16 Register Programming............................................................... 62 2 Power-Save Modes...................................................................... 16 I C Sequencer.............................................................................. 62 2 Reset Control .............................................................................. 16 I C Register Maps ........................................................................... 63 2P Global Pin Control ..................................................................... 17 I C Register Map Details ........................................................... 116H67 2 Global Status Registers................................................................... 19 51HI C Interrupt Register Map ....................................................... 117H68 2 Identification............................................................................... 19 52HI C Programming Examples.......................................................... 118H90 Status 1 ......................................................................................... 19 53HExamples Using 28 MHz Clock................................................ 90119H SD Autodetection Result ........................................................... 19 54HExamples Using 27 MHz Clock................................................ 94120H Status 2 ......................................................................................... 19 55HPCB Layout Recommendations.................................................... 121H97 Status 3 ......................................................................................... 19 56HAnalog Interface Inputs............................................................. 97122H Standard Definition Processor (SDP).......................................... 20 P57H ower Supply Decoupling ......................................................... 97123H SD Luma Path ............................................................................. 20 P58H LL ............................................................................................... 124H97 SD Chroma Path......................................................................... 20 Dig59H ital Outputs (Both Data and Clocks) ................................ 125H97 Sync Processing........................................................................... 21 60HDigital Inputs .............................................................................. 98126H VBI Data Recovery..................................................................... 21 61HAntialiasing Filters ..................................................................... 98127H Rev. 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