Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs ADV7320/ADV7321 On-board voltage reference FEATURES Six 12-bit NSV (noise shaped video) precision video DACs High definition (HD) input formats 2 2-wire serial I C interface, open-drain configuration 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Dual I/O supply 2.5 V/3.3 V operation Fully compliant with Analog and digital supply 2.5 V SMPTE 274M (1080i, 1080p 74.25 MHz) On-board PLL SMPTE 296M (720p) 64-lead LQFP package SMPTE 240M (1035i) Lead (Pb) free product RGB in 3-bit 10-bit 4:4:4 input format HDTV RGB supported APPLICATIONS RGB, RGBHV EVD (enhanced versatile disk) players Other HD formats using async timing mode High-end SD/PS DVD recorders/players Enhanced definition (ED) input formats SD/PS/HDTV display devices 8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb SD/HDTV set top boxes SMPTE 293M (525p) Professional video systems BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) FUNCTIONAL BLOCK DIAGRAM ITU-R BT.1362 (625p/525p) RGB in 3-bit 10-bit 4:4:4 input format STANDARD DEFINITION ADV7320/ Standard definition (SD) input formats CONTROL BLOCK ADV7321 CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input COLOR CONTROL BRIGHTNESS HD output formats DNR 12-BIT GAMMA DAC YPrPb HDTV (EIA 770.3) PROGRAMMABLE FILTERS O 12-BIT RGB, RGBHV SD TEST PATTERN V DAC E CGMS-A (720p/1080i) R D 12-BIT Y9Y0 S E DAC ED output formats PROGRAMMABLE C9C0 A M RGB MATRIX S9S0 M U Macrovision Rev 1.2 (525p/625p) (ADV7320 only) 12-BIT P X DAC L CGMS-A (525p/625p) I N HIGH DEFINITION 12-BIT YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2) G CONTROL BLOCK DAC RGB, RGBHV HD TEST PATTERN 12-BIT DAC SD output formats COLOR CONTROL HSYNC ADAPTIVE FILTER CTRL TIMING VSYNC Composite NTSC M/N SHARPNESS FILTER GENERATOR BLANK Composite PAL M/N/B/D/G/H/I, PAL-60 2 I C INTERFACE CLKIN A SMPTE 170M NTSC-compatible composite video PLL CLKIN B ITU-R BT.470 PAL-compatible composite video Figure 1. S-video (Y/C) EuroScart RGB GENERAL DESCRIPTION Component YPrPb (Betacam, MII, SMPTE/EBU N10) The ADV7320/ADV7321 are high speed, digital-to-analog Macrovision Rev 7.1.L1 (ADV7320 only) encoders on single monolithic chips. They include six high CGMS/WSS speed NSV video DACs with TTL-compatible inputs. They have Closed captioning separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept data in high definition (HD) and/or standard definition (SD) GENERAL FEATURES video format. For all standards, external horizontal, vertical, Simultaneous SD/HD or PS/SD inputs and outputs and blanking signals, or EAV/SAV timing codes, control the Oversampling up to 216 MHz insertion of appropriate synchronization signals into the digital Programmable DAC gain control data stream and, therefore, the output signal. Sync outputs in all modes Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05067-001ADV7320/ADV7321 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Sequence ........................................................................... 45 General Features ............................................................................... 1 SD VCR FF/RW Sync ................................................................ 45 Applications....................................................................................... 1 Vertical Blanking Interval ......................................................... 46 Functional Block Diagram .............................................................. 1 Subcarrier Frequency Registers................................................ 46 General Description ......................................................................... 1 Square Pixel Timing Mode........................................................ 47 Revision History ............................................................................... 3 Filters............................................................................................ 48 Detailed Features .............................................................................. 4 Color Controls and RGB Matrix .............................................. 49 Terminology ...................................................................................... 5 Programmable DAC Gain Control .......................................... 53 Specifications..................................................................................... 6 Gamma Correction .................................................................... 53 Dynamic Specifications ............................................................... 7 HD Sharpness Filter and Adaptive Filter Controls................ 55 Timing Specifications .................................................................. 8 HD Sharpness Filter and Adaptive Filter Application Examples ..................................... 56 Timing Diagrams.......................................................................... 9 SD Digital Noise Reduction...................................................... 57 Absolute Maximum Ratings.......................................................... 16 Coring Gain Border ................................................................... 58 Thermal Characteristics ............................................................ 16 Coring Gain Data ....................................................................... 58 ESD Caution................................................................................ 16 DNR Threshold .......................................................................... 58 Pin Configuration and Function Descriptions........................... 17 Border Area................................................................................. 58 Typical Performance Characteristics ........................................... 19 Block Size Control...................................................................... 58 MPU Port Description................................................................... 23 DNR Input Select Control......................................................... 58 Register Access................................................................................ 25 DNR Mode Control ................................................................... 59 Register Programming............................................................... 25 Block Offset Control.................................................................. 59 Subaddress Register (SR7 to SR0) ............................................ 25 SD Active Video Edge................................................................ 59 Input Configuration ....................................................................... 38 SAV/EAV Step-Edge Control ................................................... 59 SD Only........................................................................................ 38 / Output Control ............................................ 61 HSYNC VSYNC PS Only or HDTV Only ............................................................ 38 Board Design and Layout.............................................................. 62 Simultaneous SD/PS or SD/HDTV.......................................... 38 DAC Termination and Layout Considerations ...................... 62 PS at 27 MHz (Dual Edge) or 54 MHz .................................... 39 Video Output Buffer and Optional Output Filter.................. 62 Features ............................................................................................ 41 PCB Board Layout...................................................................... 63 Output Configuration................................................................ 41 Appendix 1Copy Generation Management System .............. 65 HD Async Timing Mode........................................................... 42 PS CGMS..................................................................................... 65 HD Timing Reset........................................................................ 43 HD CGMS................................................................................... 65 SD Real-Time Control, Subcarrier Reset, and Timing Reset ....43 SD CGMS .................................................................................... 65 Rev. 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