DS1284/DS1286 Watchdog Timekeepers www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS1284/DS1286 watchdog timekeepers are Keeps Track of Hundredths of Seconds, self-contained real-time clocks, alarms, watchdog Seconds, Minutes, Hours, Days, Date of the timers, and interval timers in a 28-pin JEDEC DIP Month, Months, and Years Valid Leap Year and encapsulated DIP package. The DS1286 Compensation Up to 2100 contains an embedded lithium energy source and a Watchdog Timer Restarts an Out-of-Control quartz crystal, which eliminates the need for any Processor external circuitry. The DS1284 requires an external Alarm Function Schedules Real-Time-Related quartz crystal and a V source, which could be a Activities BAT lithium battery. Data contained within 64 8-bit Embedded Lithium Energy Cell Maintains registers can be read or written in the same manner Time, Watchdog, User RAM, and Alarm as byte-wide static RAM. Data is maintained in the Information watchdog timekeeper by intelligent control circuitry Programmable Interrupts and Square-Wave that detects the status of V and write protects Outputs Maintain JEDEC Footprint CC memory when V is out of tolerance. The lithium All Registers are Individually Addressable via CC energy source can maintain data and real time for the Address and Data Bus over 10 years in the absence of V . Watchdog Accuracy is Better than 1 Minute/Month at CC timekeeper information includes hundredths of +25C (EDIP) seconds, seconds, minutes, hours, day, date, month, Greater than 10 Years of Timekeeping in the and year. The date at the end of the month is Absence of V CC automatically adjusted for months with fewer than 50 Bytes of User NV RAM 31 days, including correction for leap year. The Underwriters Laboratory (UL) Recognized DS1284/DS1286 operate in either 24-hour or 12- -40C to +85C Industrial Temperature Range hour format with an AM/PM indicator. The devices Option provide alarm windows and interval timing between 0.01 seconds and 99.99 seconds. The real-time Pin Configurations appear at end of data sheet. alarm provides for preset times of up to one week. ORDERING INFORMATION PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK* DS1284 0C to +70C 5.0 28 DIP (600 mils) DS1284 DS1284N -40C to +85C 5.0 28 DIP (600 mils) DS1284 N DS1284Q 0C to +70C 5.0 28 PLCC DS1284Q 0C to +70C 5.0 DS1284Q+ 28 PLCC DS1284Q DS1284Q/T&R 0C to +70C 5.0 28 PLCC/Tape and Reel DS1284Q DS1284Q+T&R 0C to +70C 5.0 28 PLCC/Tape and Reel DS1284Q DS1284QN -40C to +85C 5.0 28 PLCC DS1284QN -40C to +85C 5.0 DS1284QN+ 28 PLCC DS1284QN DS1284QN/T&R -40C to +85C 5.0 28 PLCC/Tape and Reel DS1284QN DS1284QN+T&R -40C to +85C 5.0 28 PLCC/Tape and Reel DS1284QN DS1286 0C to +70C 5.0 28 EDIP (720 mils) DS1286 -40C to +85C 5.0 DS1286I 28 EDIP (720 mils) DS1286 IND DS1286I+ -40C to +85C 5.0 28 EDIP (720 mils) DS1286 IND + Denotes a lead(Pb)-free/RoHS-compliant package. * A + anywhere on the top mark indicates a lead-free package. 1 of 18 REV: 032406 DS1284/DS1286 OPERATIONREAD REGISTERS The DS1284/DS1286 execute a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) and OE (output enable) are active (low). The unique address specified by the six address inputs (A0A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight data output drivers within t (access time) after the last address input signal is stable, provided that CE and ACC OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either t for CE or t CO OE for OE rather than address access. OPERATIONWRITE REGISTERS The DS1284/DS1286 are in the write mode whenever the WE and CE signals are in the active-low state after the address inputs are stable. The latter occurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state (t ) before another cycle can be initiated. Data must be valid on the data bus with sufficient data WR setup (t ) and data hold time (t ) with respect to the earlier rising edge of CE or WE. The OE control DS DH signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION The watchdog timekeeper provides full functional capability when V is greater than V . Data is CC TP maintained in the absence of V without any additional support circuitry. The DS1284/DS1286 CC constantly monitor V . Should the supply voltage decay, the watchdog timekeeper automatically write CC protects itself, and all inputs to the registers become dont care. Both INTA and INTB (INTB) are open-drain outputs. The two interrupts and the internal clock continue to run regardless of the level of V . However, it is important to ensure that the pullup resistors used with the interrupt pins are never CC pulled up to a value greater than V + 0.3V. As V falls below the battery voltage, a power-switching CC CC circuit turns on the lithium energy source to maintain the clock and timer data functionality. Also ensure that during this time (battery-backup mode), the voltage present at INTA and INTB (INTB) never exceeds the battery voltage. If the active-high mode is selected for INTB (INTB), this pin only goes high in the presence of V . During power-up, when V rises above approximately 3.0V, the power-switching CC CC circuit connects external V and disconnects the V energy source. Normal operation can resume after CC BAT V exceeds V for t . CC TP REC WATCHDOG TIMEKEEPER REGISTERS The watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog, control, and data information. The clock, calendar, alarm, and watchdog registers are memory locations that contain external (user-accessible) and internal copies of the data. The external copies are independent of internal functions, except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The command register bits are affected by both internal and external functions. This register is discussed later. The 50 bytes of RAM registers can only be accessed from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day and date information (see Figure 2). Time-of-day information is stored in binary-coded decimal (BCD). Registers 3, 5, and 7 contain the time-of-day alarm information. Time-of-day alarm information is stored in BCD. Register B is the command register and information in this register is binary. Registers C and D are the watchdog alarm registers and information stored in these two registers is in BCD. Registers E to 3F are user bytes and can be used to contain data at the users discretion. 2 of 18