DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs FEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and TOP VIEW Lithium Energy Source N.C. 1 28 V CC DS1743 Clock Registers are Accessed Identically to A12 2 27 WE A7 3 26 CE2 the Static RAM. These Registers Reside in A6 4 25 A8 A5 5 24 the Eight Top RAM Locations. A9 A4 6 23 A11 Century Byte Register A3 7 22 OE Totally Nonvolatile with Over 10 Years of A2 8 21 A10 A1 9 20 CE Operation in the Absence of Power A0 10 19 DQ7 BCD-Coded Century, Year, Month, Date, DQ0 11 18 DQ6 DQ1 12 17 DQ5 Day, Hours, Minutes, and Seconds with DQ2 13 16 DQ4 Automatic Leap Year Compensation Valid GND 14 15 DQ3 through 2099 28-Pin Encapsulated Package Low-Battery-Voltage Level Indicator Flag (28 PIN 740) Power-Fail Write Protection Allows for 10% V Power-Supply Tolerance CC Lithium Energy Source is Electrically 34 N.C. 1 N.C. DS1743P Disconnected to Retain Freshness Until 2 33 N.C. N.C. 32 N.C. 3 N.C. Power is Applied for the First Time 31 4 N.C. RST 30 5 A12 V CC DIP Module Only 6 29 A11 WE 7 28 A10 OE Standard JEDEC Bytewide 8k x 8 Static 27 A9 8 CE 26 A8 9 RAM Pinout DQ7 25 10 A7 DQ6 PowerCap Module Board Only 24 A6 11 DQ5 23 12 A5 DQ4 Surface-Mountable Package for Direct 22 A4 13 DQ3 14 21 A3 DQ2 Connection to PowerCap Containing 20 A2 15 DQ1 19 A1 16 DQ0 Battery and Crystal GND V BAT X2 X1 18 17 A0 GND Replaceable Battery (PowerCap) 34-Pin PowerCap Module Board Power-On Reset Output (Uses DS9034PCX+ or DS9034I-PCX+ PowerCap) Pin-for-Pin Compatible with Other Densities of DS174XP Timekeeping RAM Underwriters Laboratories (UL) Recognized to Prevent Charging of the Internal Lithium Battery N ote: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maximintegrated.com/errata. 1 of 17 19-6719 Rev 9/13 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs PIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enable, 1 N.C. No Connection 20 8 CE 3134 Active Low 2 30 A12 21 28 A10 Address Input 3 25 A7 Output Enable, 22 7 OE Active Low 4 24 A6 23 29 A11 5 23 A5 24 27 A9 Address Input 6 22 A4 Address Input 25 26 A8 7 21 A3 26 CE2 Chip Enable 2 8 20 A2 Write Enable, 9 19 A1 27 6 WE Active Low 10 18 A0 Power-Supply 28 5 V 11 16 DQ0 CC Input Data Input/ 12 15 DQ1 Power-On Reset Output 13 14 DQ2 4 RST Output, Active 14 17 GND Ground Low Crystal 15 13 DQ3 X1, X2 Connection 16 12 DQ4 Data Input/ Battery 17 11 DQ5 V BAT Output Connection 18 10 DQ6 19 9 DQ7 2 of 17