Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators Data Sheet ADCMP606/ADCMP607 FEATURES GENERAL DESCRIPTION Fully specified rail to rail at V = 2.5 V to 5.5 V The ADCMP606 and ADCMP607 are very fast comparators CCI Input common-mode voltage from 0.2 V to V + 0.2 V CCI fabricated on XFCB2, an Analog Devices, Inc., proprietary CML-compatible output stage process. These comparators are exceptionally versatile and easy 1.25 ns propagation delay to use. Features include an input range from VEE 0.5 V to 50 mW at 2.5 V power supply VCCI + 0.2 V, low noise, CML-compatible output drivers, and Shutdown pin TTL-/CMOS-compatible latch inputs with adjustable hysteresis Single-pin control for programmable hysteresis and latch and/or shutdown inputs. (ADCMP607 only) The devices offer 1.25 ns propagation delay with 2.5 ps rms Power supply rejection > 60 dB random jitter (RJ). Overdrive and slew rate dispersion are 40C to +125C operation typically less than 50 ps. APPLICATIONS A flexible power supply scheme allows the devices to operate High speed instrumentation with a single +2.5 V positive supply and a 0.5 V to +2.7 V Clock and data signal restoration input signal range up to a +5.5 V positive supply with a 0.5 V Logic level shifting or translation to +5.7 V input signal range. The ADCMP607 features split Pulse spectroscopy input/output supplies with no sequencing restrictions to High speed line receivers support a wide input signal range with independent output Threshold detection swing control and power savings. Peak and zero-crossing detectors The CML-compatible output stage is fully back-matched for High speed trigger circuitry superior performance. The comparator input stage offers robust Pulse-width modulators protection against large input overdrive, and the outputs do not Current-/voltage-controlled oscillators phase reverse when the valid input signal range is exceeded. On Automatic test equipment (ATE) the ADCMP607, latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package and the ADCMP607 is available in a 12-lead LFCSP package. FUNCTIONAL BLOCK DIAGRAM V CCO V (ADCMP607 ONLY) CCI V NONINVERTING P INPUT Q OUTPUT CML ADCMP606/ ADCMP607 Q OUTPUT V INVERTING N INPUT LE/HYS INPUT (ADCMP607 ONLY) S INPUT (ADCMP607 ONLY) DN Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. 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Technical Support www.analog.com 05917-001ADCMP606/ADCMP607 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 10 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 10 General Description ......................................................................... 1 CML-Compatible Output Stage ............................................... 10 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature ........................................... 10 Revision History ............................................................................... 2 Optimizing Performance ........................................................... 10 Specifications ..................................................................................... 3 Comparator Propagation Delay Dispersion ............................... 11 Electrical Characteristics ............................................................. 3 Comparator Hysteresis .............................................................. 11 Timing Information ..................................................................... 5 Crossover Bias Points ................................................................. 12 Absolute Maximum Ratings ............................................................ 6 Minimum Input Slew Rate Requirement ................................ 12 Thermal Resistance ...................................................................... 6 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 4/16Rev. B to Rev. C Changes to Figure 4 and Table 6 ..................................................... 7 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 11/14Rev. A to Rev. B Changes to Figure 4 and Table 6 ..................................................... 7 Changes to Figure 12 and Figure 13 ............................................... 9 Changes to Comparator Hysteresis Section ................................ 11 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 8/07Rev. 0 to Rev. A Changes to Specifications Section .................................................. 3 Changes to Table 3 ............................................................................ 6 Changes to Ordering Guide .......................................................... 14 10/06Revision 0: Initial Version Rev. C Page 2 of 14