X-On Electronics has gained recognition as a prominent supplier of EVAL-ADF7023-JDB3Z Sub-GHz Development Tools across the USA, India, Europe, Australia, and various other global locations. EVAL-ADF7023-JDB3Z Sub-GHz Development Tools are a product manufactured by Analog Devices. We provide cost-effective solutions for Sub-GHz Development Tools, ensuring timely deliveries around the world.

EVAL-ADF7023-JDB3Z Analog Devices

EVAL-ADF7023-JDB3Z electronic component of Analog Devices
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Part No.EVAL-ADF7023-JDB3Z
Manufacturer: Analog Devices
Category: Sub-GHz Development Tools
Description: Sub-GHz Development Tools Daughterboard, 902-958MHz
Datasheet: EVAL-ADF7023-JDB3Z Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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We are delighted to provide the EVAL-ADF7023-JDB3Z from our Sub-GHz Development Tools category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the EVAL-ADF7023-JDB3Z and other electronic components in the Sub-GHz Development Tools category and beyond.

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High Performance, Low Power, ISM Band FSK/GFSK/MSK/GMSK Transceiver IC Data Sheet ADF7023-J FEATURES SPORT mode support High speed synchronous serial interface to Tx and Rx Data Ultralow power, high performance transceiver for direct interfacing to processors and DSPs Frequency bands: 902 MHz to 958 MHz Packet management support Data rates supported: 1 kbps to 300 kbps Highly flexible for a wide range of packet formats 2.2 V to 3.6 V power supply Insertion/detection of preamble/sync word/CRC/address Single-ended and differential power amplifiers (PAs) Manchester and 8b/10b data encoding and decoding Low IF receiver with programmable IF bandwidths Data whitening 100 kHz, 150 kHz, 200 kHz, 300 kHz Smart wake mode Receiver sensitivity (BER) Current saving low power mode with autonomous receiver 116 dBm at 1.0 kbps, 2FSK, GFSK wake up, carrier sense, and packet reception 107.5 dBm at 38.4 kbps, 2FSK, GFSK Downloadable firmware modules 106.5 dBm at 50 kbps, 2FSK, GFSK Image rejection calibration, fully automated (patent 105 dBm at 100 kbps, 2FSK, GFSK pending) 104 dBm at 150 kbps, GFSK, GMSK 128-bit AES encryption/decryption with hardware 103 dBm at 200 kbps, GFSK, GMSK acceleration and key sizes of 128 bits, 192 bits, and 100.5 dBm at 300 kbps, GFSK, GMSK 256 bits Very low power consumption Reed-Solomon error correction with hardware acceleration 12.8 mA in PHY RX mode (maximum front-end gain) 240-byte packet buffer for Tx/Rx data 11.9 mA in PHY RX mode (AGC off, ADC off) Efficient SPI control interface with block read/write access 24.1 mA in PHY TX mode (10 dBm output, single-ended PA) Integrated battery alarm and temperature sensor 0.75 A in PHY SLEEP mode (32 kHz RC oscillator active) Integrated RC and 32.768 kHz crystal oscillator 1.28 A in PHY SLEEP mode (32 kHz XTAL oscillator active) On-chip, 8-bit ADC 0.33 A in PHY SLEEP mode (Deep Sleep Mode 1) 5 mm 5 mm, 32-lead, LFCSP package RF output power of 20 dBm to +13.5 dBm (single-ended PA) RF output power of 20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) APPLICATIONS Digital received signal strength indication (RSSI) Smart metering Integrated PLL loop filter and Tx/Rx switch IEEE 802.15.4g Fast automatic voltage controlled oscillator (VCO) calibration Home automation Automatic synthesizer bandwidth optimization Process and building control On-chip, low power, custom 8-bit processor Wireless sensor networks (WSNs) Radio control Wireless healthcare Packet management Smart wake mode Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADF7023-J Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interrupts in Sport Mode .......................................................... 48 Applications ....................................................................................... 1 ADF7023-J Memory Map ............................................................. 49 Revision History ............................................................................... 3 BBRAM ........................................................................................ 49 Functional Block Diagram .............................................................. 4 Modem Configuration RAM (MCR) ...................................... 49 General Description ......................................................................... 4 Program ROM ............................................................................ 49 Specifications ..................................................................................... 6 Program RAM ............................................................................ 49 RF and Synthesizer Specifications .............................................. 6 Packet RAM ................................................................................ 50 Transmitter Specifications ........................................................... 7 SPI Interface .................................................................................... 51 Receiver Specifications ................................................................ 9 General Characteristics ............................................................. 51 Timing and Digital Specifications ............................................ 12 Command Access ....................................................................... 51 Auxilary Block Specifications ................................................... 13 Status Word ................................................................................. 51 General Specifications ............................................................... 14 Command Queuing ................................................................... 52 Timing Specifications ................................................................ 15 Memory Access ........................................................................... 53 Absolute Maximum Ratings .......................................................... 16 Low Power Modes .......................................................................... 56 ESD Caution ................................................................................ 16 Example Low Power Modes ...................................................... 59 Pin Configuration and Function Descriptions ........................... 17 Low Power Mode Timing Diagrams ........................................ 61 Typical Performance Characteristics ........................................... 19 WUC Setup ................................................................................. 62 Terminology .................................................................................... 26 Firmware Timer Setup ............................................................... 63 Radio Control .................................................................................. 27 Calibrating the RC Oscillator ................................................... 63 Radio States ................................................................................. 27 Downloadable Firmware Modules ............................................... 65 Initialization ................................................................................ 29 Writing a Module to Program RAM ........................................ 65 Commands .................................................................................. 30 Image Rejection Calibration Module ...................................... 65 Automatic State Transitions ...................................................... 32 AES Encryption and Decryption Module............................... 65 State Transition and Command Timing .................................. 33 Reed-Solomon Coding Module ............................................... 65 Sport Mode ...................................................................................... 37 Radio Blocks .................................................................................... 67 Packet Structure in Sport Mode ............................................... 37 Frequency Synthesizer ............................................................... 67 Sport Mode in Transmit ............................................................ 37 Crystal Oscillator ........................................................................ 68 Sport Mode in Receive ............................................................... 37 Modulation .................................................................................. 68 Transmit Bit Latencies in Sport Mode ..................................... 37 RF Output Stage.......................................................................... 69 Packet Mode .................................................................................... 40 PA/LNA Interface ....................................................................... 69 Preamble ...................................................................................... 40 Receive Channel Filter ............................................................... 69 Sync Word ................................................................................... 41 Image Channel Rejection .......................................................... 69 Payload ......................................................................................... 42 Automatic Gain Control (AGC) ............................................... 70 CRC .............................................................................................. 43 RSSI .............................................................................................. 70 Postamble..................................................................................... 44 2FSK/GFSK/MSK/GMSK Demodulation ............................... 72 Transmit Packet Timing ............................................................ 44 Clock Recovery ........................................................................... 73 Data Whitening .......................................................................... 45 Recommended Receiver Settings for 2FSK/GFSK/MSK/GMSK ......................................................... 73 Manchester Encoding ................................................................ 45 Peripheral Features ......................................................................... 76 8b/10b Encoding ........................................................................ 45 Analog-to-Digital Converter .................................................... 76 Interrupt Generation ...................................................................... 46 Rev. D Page 2 of 104

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