High Performance, 3.2 GHz, 14-Output Fanout Buffer Data Sheet HMC7043 The HMC7043 is designed to meet the requirements of multicarrier FEATURES GSM and LTE base station designs, and offers a wide range of JEDEC JESD204B support clock management and distribution features to simplify baseband Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz) and radio card clock tree designs. Very low noise floor: 155.2 dBc/Hz at 983.04 MHz Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) The HMC7043 provides 14 low noise and configurable outputs Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx to offer flexibility in interfacing with many different components in frequency of 3200 MHz a base transceiver station (BTS) system, such as data converters, JESD204B-compatible system reference (SYSREF) pulses local oscillators, transmit/receive modules, field programmable 25 ps analog and clock input cycle digital delay gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 independently programmable on each of 14 clock can generate up to seven DCLK and SYSREF clock pairs per the output channels JESD204B interface requirements. SPI-programmable adjustable noise floor vs. power consumption The system designer can generate a lower number of DCLK and SYSREF valid interrupt to simplify JESD204B synchronization SYSREF pairs, and configure the remaining output signal paths Supports deterministic synchronization of multiple for independent phase and frequency. Both the DCLK and SYSREF HMC7043 devices clock outputs can be configured to support different signaling RFSYNCIN pin or SPI-controlled SYNC trigger for output standards, including CML, LVDS, LVPECL, and LVCMOS, and synchronization of JESD204B different bias conditions to adjust for varying board insertion losses. GPIO alarm/status indicator to determine system health One of the unique features of the HMC7043 is the independent Clock input to support up to 6 GHz flexible phase management of each of the 14 channels. All 48-lead, 7 mm 7 mm LFCSP package 14 channels feature both frequency and phase adjustment. The APPLICATIONS outputs can also be programmed for 50 or 100 internal and JESD204B clock generation external termination options. Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) The HMC7043 device features an RF SYNC feature that synchro- Data converter clocking nizes multiple HMC7043 devices deterministically, that is, ensures Phase array reference distribution that all clock outputs start with the same edge. This operation is Microwave baseband cards achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output GENERAL DESCRIPTION dividers with this new phase. The HMC7043 is a high performance clock buffer for the The HMC7043 is offered in a 48-lead, 7 mm 7 mm LFCSP distribution of ultralow phase noise references for high speed data package with an exposed pad connected to ground. converters with either parallel or serial (JESD204B type) interfaces. FUNCTIONAL BLOCK DIAGRAM CLKOUT0 CLKIN/ CLKOUT0 CLKIN SCLKOUT1 SCLKOUT1 CLKOUT12 CLKOUT12 SCLKOUT13 SCLKOUT13 RFSYNCIN/ SYSREF CONTROL RFSYNCIN SPI 14-CLOCK CONTROL SDATA DISTRIBUTION INTERFACE SLEN SCLK Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 13114-001HMC7043 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 14 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 15 General Description ......................................................................... 1 Detailed Block Diagram ............................................................ 16 Functional Block Diagram .............................................................. 1 Clock Input Network ................................................................. 16 Revision History ............................................................................... 2 Clock Output Network .............................................................. 17 Specifications ..................................................................................... 3 Typical Programming Sequence............................................... 23 Conditions ..................................................................................... 3 Power Supply Considerations ................................................... 24 Supply Current .............................................................................. 3 Serial Control Port ......................................................................... 27 Digital Input/Output (I/O) Electrical Specifications ............... 4 Serial Port Interface (SPI) Control ........................................... 27 Clock Input Path Specifications.................................................. 4 Control Registers ............................................................................ 28 Additive Jitter and Phase Noise Characteristics ....................... 5 Control Register Map ................................................................ 28 Clock Output Distribution Specifications ................................. 5 Control Register Map Bit Descriptions ................................... 33 Clock Output Driver Characteristics ......................................... 6 Applications Information .............................................................. 41 Absolute Maximum Ratings ............................................................ 8 Evaluation PCB And Schematic ............................................... 41 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 43 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 43 Typical Performance Characteristics ........................................... 11 Typical Application Circuits .......................................................... 13 REVISION HISTORY 7/2016Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 5/2016Rev. 0 to Rev. A Changes to Table 3 ............................................................................. 4 Change to Maximum Operating Frequency Parameter, Table 7 ..... 7 Added Figure 6, Renumbered Sequentially ................................ 11 Change to Synchronization FSM/Pulse Generator Timing Section ................................................................................. 21 Changes to Table 20 ........................................................................ 28 Change to Table 22 ......................................................................... 33 Changes to Table 28 ........................................................................ 34 Changes to Table 29 ........................................................................ 35 Change to Table 31 ......................................................................... 36 Change to Table 38 ......................................................................... 37 Changes to Table 41 ........................................................................ 39 12/2015Revision 0: Initial Version Rev. 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