25 MHz to 3000 MHz Fractional-N PLL with Integrated VCO Data Sheet HMC832A FEATURES FUNCTIONAL BLOCK DIAGRAM LD/SDO SCK SDI RF bandwidth: 25 MHz to 3000 MHz 3.3 V supply HMC832A LOCK DETECT Maximum phase detector rate: 100 MHz SPI Ultralow phase noise SEN CONTROL PROGRAMMING INTERFACE 110 dBc/Hz in band (typical), f at 1600 MHz O EN Fractional figure of merit (FOM): 226 dBc/Hz MODULATOR CAL RF P 24-bit step size, 3 Hz typical resolution EN RF N Exact frequency mode with 0 Hz frequency error Fast frequency hopping 1, 2, 4, 6, ...62 2 40-lead, 6 mm 6 mm LFCSP package: 36 mm N APPLICATIONS VCO CP CP PFD VTUNE Cellular infrastructure R Microwave radios WiMax, WiFi Communications test equipment XREFP CATV equipment Figure 1. DDS replacement Military Tunable reference sources for spurious-free performance GENERAL DESCRIPTION The HMC832A is a 3.3 V, high performance, wideband, frac- The HMC832A is footprint compatible to the HMC830 PLL tional-N, phase-locked loop (PLL) that features an integrated with an integrated VCO. It features 3.3 V supply and innovative voltage controlled oscillator (VCO) with a fundamental programmable performance technology that enables the frequency of 1500 MHz to 3000 MHz and an integrated VCO HMC832A to tailor current consumption and corresponding output divider (divide by 1, 2, 4, 6, 62) that enables the noise floor performance to individual applications by selecting HMC832A to generate continuous frequencies from 25 MHz to either a low current consumption mode or a high performance mode for improved noise floor performance. 3000 MHz. The integrated phase detector (PD) and - modulator, capable of operating at up to 100 MHz, permit wider Additional features of the HMC832A include 12 dB of RF loop bandwidths and faster frequency tuning with excellent output gain control in 1 dB steps an output mute function to spectral performance. automatically mute the output during frequency changes when Industry leading phase noise and spurious performance, across the device is not locked selectable output return loss all frequencies, enable the HMC832A to minimize blocker programmable differential or single-ended outputs, with the effects, and to improve receiver sensitivity and transmitter ability to select either output in single-ended mode a - spectral purity. A low noise floor (160 dBc/Hz eliminates any modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error and a register contribution to modulator/mixer noise floor in transmitter applications. configurable 3.3 V or 1.8 V serial port interface (SPI). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 13110-001HMC832A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ID, Read Address, and Reset (RST) Registers ........................ 35 Applications ....................................................................................... 1 Reference Divider (REFDIV), Integer, and Fractional Frequency Registers ................................................................... 35 Functional Block Diagram .............................................................. 1 VCO SPI Register ....................................................................... 36 General Description ......................................................................... 1 - Configuration Register ...................................................... 36 Revision History ............................................................................... 2 Lock Detect Register .................................................................. 37 Specifications ..................................................................................... 3 Analog Enable (EN) Register .................................................... 37 Timing Specifications .................................................................. 6 Charge Pump Register ............................................................... 38 Absolute Maximum Ratings ............................................................ 7 Autocalibration Register ............................................................ 38 Recommended Operating Conditions ...................................... 7 Phase Detector (PD) Register ................................................... 39 ESD Caution .................................................................................. 7 Exact Frequency Mode Register ............................................... 39 Pin Configuration and Function Descriptions ............................. 8 General-Purpose, SPI, and Reference Divider Typical Performance Characteristics ............................................. 9 (GPO SPI RDIV) Register ...................................................... 40 Theory of Operation ...................................................................... 15 VCO Tune Register .................................................................... 41 PLL Subsystem Overview .......................................................... 15 Sucessive Approximation Register ........................................... 41 VCO Subsystem Overview ........................................................ 15 General-Purpose 2 Register ...................................................... 41 SPI Configuration of PLL and VCO Subsystems ................... 15 Built-In Self Test (BIST) Register ............................................. 41 VCO Subsystem .......................................................................... 17 VCO Subsystem Register Map ...................................................... 42 PLL Subsystem ............................................................................ 21 VCO Enable Register ................................................................. 42 Soft Reset and Power-On Reset ................................................ 28 VCO Output Divider Register .................................................. 43 Power-Down Mode .................................................................... 28 VCO Configuration Register .................................................... 43 General-Purpose Output (GPO) .............................................. 28 VCO Calibration/Bias, Center Frequency Calibration Chip Identification ..................................................................... 29 (CF CAL), and MSB Calibration Registers ............................ 44 Serial Port Interface (SPI) .......................................................... 29 VCO Output Power Control ..................................................... 44 Applications Information .............................................................. 32 Evaluation Printed Circuit Board (PCB) ..................................... 45 Power Supply ............................................................................... 33 Changing Evaluation Board Reference Frequency and CP Programmable Performance Technology ................................ 33 Current Configuration .............................................................. 46 Loop Filter and Frequency Changes ........................................ 33 Evaluation Kit Contents ............................................................ 46 RF Programmable Output Return Loss ................................... 34 Outline Dimensions ....................................................................... 47 Mute Mode .................................................................................. 34 Ordering Guide .......................................................................... 48 PLL Register Map ........................................................................... 35 REVISION HISTORY 11/15Revision B: Initial Version Rev. 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