EVALUATION KIT AVAILABLE MAX1510/MAX17510 Low-Voltage DDR Linear Regulators General Description Features The MAX1510/MAX17510 DDR linear regulators source Internal Power MOSFETs with Current Limit (3A typ) and sink up to 3A peak (typ) using internal n-channel Fast Load-Transient Response MOSFETs. These linear regulators deliver an accurate External Reference Input with Reference Output 0.5V to 1.5V output from a low-voltage power input (V = Buffer IN 1.1V to 3.6V). The MAX1510/MAX17510 use a separate 1.1V to 3.6V Power Input 3.3V bias supply to power the control circuitry and drive 15mV (max) Load-Regulation Error the internal n-channel MOSFETs. Thermal-Fault Protection The MAX1510/MAX17510 provide current and thermal Shutdown Input limits to prevent damage to the linear regulator. Additionally, Power-Good Window Comparator with 2ms (typ) the MAX1510/MAX17510 generate a power-good Delay (PGOOD) signal to indicate that the output is in regulation. Small, Low-Profile 10-Pin, 3mm x 3mm TDFN During startup, PGOOD remains low until the output is in Package regulation for 2ms (typ). The internal soft-start limits the Ceramic or Polymer Output Capacitors input surge current. The MAX1510/MAX17510 power the active-DDR Ordering Information termination bus that requires a tracking input reference. The devices can also be used in low-power chipsets PIN- TOP PART TEMP RANGE and graphics processor cores that require dynamically PACKAGE MARK adjustable output voltages. The MAX1510/MAX17510 are MAX1510ETB -40C to +85C 10 TDFN-EP* ARD available in a 10-pin, 3mm x 3mm thin DFN package. MAX1510ETB+ -40C to +85C 10 TDFN-EP* ABD Applications MAX1510ATB/V+ -40C to +85C 10 TDFN-EP* AWD Notebook/Desktop Computers MAX17510ATB+ -40C to +125C 10 TDFN-EP* AWQ DDR Memory Termination MAX17510ATB/V+ -40C to +125C 10 TDFN-EP* AWX Active Termination Buses +Denotes a lead(Pb)-free and RoHS-compliant package. Graphics Processor Core Supplies *EP = Exposed pad. Chipset/RAM Supplies as Low as 0.5V /V denotes an automotive qualified part. Pin Configuration Typical Operating Circuit V IN TOP VIEW (1.1V TO 3.6V) V = V OUT TT IN OUT 10 9 8 7 6 OUTS MAX1510 V BIAS MAX17510 MAX1510 (2.7V TO 3.6V) V PGND MAX17510 CC AGND SHDN + 1 2 3 4 5 PGOOD V DDQ (2.5V OR 1.8V) V = V REFOUT TTR REFIN REFOUT TDFN 3mm x 3mm A SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. 19-3279 Rev 8 1/20 REFOUT IN V OUT CC AGND PGND REFIN SHDN PGOOD OUTSMAX1510/MAX17510 Low-Voltage DDR Linear Regulators Absolute Maximum Ratings IN to PGND ..........................................................-0.3V to +4.3V Operating Temperature Range OUT to PGND ............................................-0.3V to (V + 0.3V) MAX1510ETB ................................................. -40C to +85C IN OUTS to AGND ..........................................-0.3V to (V + 0.3V) MAX17510ATB ............................................. -40C to +125C IN V to AGND .......................................................-0.3V to +4.3V Junction Temperature ......................................................+150C CC REFIN, REFOUT, SHDN, Storage Temperature Range ............................ -65C to +150C PGOOD to AGND ................................. -0.3V to (V + 0.3V) Lead Temperature (soldering, 10s) .................................+300C CC PGND to AGND ....................................................-0.3V to +0.3V Soldering Temperature (reflow) REFOUT Short Circuit to AGND ...............................Continuous Lead(Pb)-free packages ..............................................+260C OUT Continuous RMS Current: 100s .................................1.6A Packages containing lead(Pb) .....................................+240C 1s ....................................2.5A Junction-to-Ambient Thermal Resistance (JA) ..............41C/W Continuous Power Dissipation (T = +70C) Junction-to-Case Thermal Resistance (JC) ....................9C/W A 10-Pin 3mm x 3mm TDFN (derated 24.4mW/C above +70C) ..........................1951mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (V = 1.8V, V = 3.3V, V = V = 1.25V, SHDN = V , circuit of Figure 1, T = T = -40C to +85C for MAX1510ETB, IN CC REFIN OUTS CC J A T = T = -40C to +125C for MAX17510ATB, unless otherwise noted. Typical values are at T = +25C.) (Note 1) J A A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V Power input 1.1 3.6 IN Input-Voltage Range V V Bias supply 2.7 3.6 CC Quiescent Supply Current (V ) I Load = 0, V > 0.45V 0.7 1.3 mA CC CC REFIN SHDN = GND, V > 0.45V 350 600 REFIN Shutdown Supply Current (V ) I A CC CC(SHDN) SHDN = GND, REFIN = GND 50 100 Quiescent Supply Current (V ) I Load = 0 0.4 10 mA IN IN Shutdown Supply Current (V ) I SHDN = GND 0.1 10 A IN IN(SHDN) T = +25C -4 0 +4 A REFIN to OUTS Feedback-Voltage Error V mV OUTS I = 200mA OUT T = -40C to +125C -6 +6 A Load-Regulation Error -1A I +1A -15 +15 mV OUT Line-Regulation Error 1.4V V 3.3V, I = 100mA 1 mV IN OUT OUTS Input-Bias Current I -1 +1 A OUTS OUTPUT Output Adjust Range 0.5 1.5 V High-side MOSFET (source) (I = 0.1A) 0.14 0.25 OUT OUT On-Resistance Low-side MOSFET (sink) (I = -0.1A) 0.14 0.25 OUT Output Current Slew Rate C = 100F, I = 0.1A to 2A 3 A/s OUT OUT OUT Power-Supply Rejection 10Hz < f < 10kHz, I = 200mA, OUT PSRR 80 dB Ratio C = 100F OUT Maxim Integrated 2 www.maximintegrated.com