EVALUATION KIT AVAILABLE MAX3420E USB Peripheral Controller with SPI Interface General Description Benefits and Features The MAX3420E contains the digital logic and Simplifies Adding USB to Any System analog circuitry necessary to implement a full-speed USB Microprocessor-Independent USB Solution peripheral compliant to USB specification rev 2.0. A built- Complies with USB Specification Revision 2.0 in full-speed transceiver features 15kV ESD protection (Full-Speed Operation) and programmable USB connect and disconnect. An Integrated Full-Speed USB Transceiver internal serial-interface engine (SIE) handles low-level USB Firmware/Hardware Control of an Internal D+ protocol details such as error checking and bus retries. Pullup Resistor The MAX3420E operates using a register set accessed Programmable 3 or 4-Wire 26MHz SPI Interface by an SPI interface that operates up to 26MHz. Any SPI Intelligent USB Serial-Interface Engine (SIE) master (microprocessor, ASIC, DSP, etc.) can add USB Automatically Handles USB Flow Control and functionality using the simple 3- or 4-wire SPI interface. Double Buffering Handles Low-Level USB Signaling Details Internal level translators allow the SPI interface to run at Includes Timers for USB Time-Sensitive Operations, a system voltage between 1.71V and 3.6V. USB timed So SPI Master Does Not Need to Time Events operations are done inside the MAX3420E with interrupts Four General-Purpose Inputs and Four General- provided at completion so an SPI master does not need Purpose Outputs timers to meet USB timing requirements. The MAX3420E Internal Comparator Detects V for Self-Powered includes four general-purpose inputs and outputs so any BUS microprocessor that uses I/O pins to implement the SPI Applications interface can reclaim the I/O pins and gain additional ones. Interrupt Output Pin (Level or Programmable Edge) Allows Polled or Interrupt-Driven SPI Interface The MAX3420E operates over the extended -40C to +85C temperature range and is available in a 32-pin Double-Buffered Data Endpoints Increase LQFP package (7mm x 7mm) and a space-saving 24-pin Throughput by Allowing the SPI Master to Transfer TQFN package (4mm x 4mm). Data Concurrently with USB Transfers Over the Same Endpoint Applications Built-In Endpoint FIFOs Cell Phones EP0: CONTROL (64 Bytes) PC Peripherals EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes Microprocessors and DSPs (Double-Buffered) Custom USB Devices EP2: IN, Bulk or Interrupt, 2 x 64 Bytes Cameras (Double-Buffered) Desktop Routers EP3: IN, Bulk or Interrupt (64 Bytes) PLCs SETUP Data Has Its Own 8-Byte FIFO, Simplifying Set-Top Boxes Firmware PDAs ESD Protection on D+, D-, and VBCOMP Improves MP3 Players System Reliability Instrumentation 19-3781 Rev 6 3/16MAX3420E USB Peripheral Controller with SPI Interface Functional Diagram V L RES XI XO V CC INTERNAL POR RESET OSC LOGIC 1.5k AND PLL 4x POWER 48MHz DOWN D+ FULL-SPEED USB SIE ESD USB (SERIAL-INTERFACE ENGINE) PROTECTION D- TRANSCEIVER SCLK MOSI SPI SLAVE INTERFACE MISO ENDPOINT BUFFERS SS ESD VBCOMP VBUS DET PROTECTION INT VBUS COMP 1V TO 3V R GPIN VBUS DET OPERATE BUSACT SOF 0 1 2 3 MAX3420E MUX GND GPX GPIN2 GPIN1 GPIN0 GPOUT3 GPIN3 GPOUT1 GPOUT2 GPOUT0 Maxim Integrated 2 www.maximintegrated.com