EVALUATION KIT AVAILABLE MAX3421E USB Peripheral/Host Controller with SPI Interface General Description Features Microprocessor-Independent USB Solution The MAX3421E USB peripheral/host controller contains the digital logic and analog circuitry necessary to Software Compatible with the MAX3420E USB implement a full-speed USB peripheral or a full-/low- Peripheral Controller with SPI Interface speed host compliant to USB specification rev 2.0. A Complies with USB Specification Revision 2.0 built-in transceiver features 15kV ESD protection and (Full-Speed 12Mbps Peripheral, Full-/Low-Speed programmable USB connect and disconnect. An inter- 12Mbps/1.5Mbps Host) nal serial interface engine (SIE) handles low-level USB Integrated USB Transceiver protocol details such as error checking and bus retries. The MAX3421E operates using a register set accessed Firmware/Hardware Control of an Internal D+ by an SPI interface that operates up to 26MHz. Any SPI Pullup Resistor (Peripheral Mode) and D+/D- master (microprocessor, ASIC, DSP, etc.) can add USB Pulldown Resistors (Host Mode) peripheral or host functionality using the simple 3- or 4- Programmable 3- or 4-Wire, 26MHz SPI Interface wire SPI interface. Level Translators and V Input Allow Independent L The MAX3421E makes the vast collection of USB System Interface Voltage peripherals available to any microprocessor, ASIC, or Internal Comparator Detects V for Self- BUS DSP when it operates as a USB host. For point-to-point Powered Peripheral Applications solutions, for example, a USB keyboard or mouse inter- faced to an embedded system, the firmware that oper- ESD Protection on D+, D-, and VBCOMP ates the MAX3421E can be simple since only a Interrupt Output Pin (Level- or Programmable- targeted device is supported. Edge) Allows Polled or Interrupt-Driven SPI Internal level translators allow the SPI interface to run at Interface a system voltage between 1.4V and 3.6V. USB-timed Eight General-Purpose Inputs and Eight General- operations are done inside the MAX3421E with inter- Purpose Outputs rupts provided at completion so an SPI master does not Interrupt Signal for General-Purpose Input Pins, need timers to meet USB timing requirements. The Programmable Edge Polarity MAX3421E includes eight general-purpose inputs and outputs so any microprocessor that uses I/O pins to Intelligent USB SIE implement the SPI interface can reclaim the I/O pins Automatically Handles USB Flow Control and and gain additional ones. Double Buffering The MAX3421E operates over the extended -40C to Handles Low-Level USB Signaling Details +85C temperature range and is available in a 32-pin Contains Timers for USB Time-Sensitive TQFP package (5mm x 5mm) and a 32-pin TQFN pack- Operations so SPI Master Does Not Need to Time age (5mm x 5mm). Events Applications Space-Saving Lead-Free TQFP and TQFN Packages (5mm x 5mm) Embedded Systems Desktop Routers Medical Devices PLCs Microprocessors and Set-Top Boxes Ordering Information DSPs PDAs PIN- TOP Custom USB Devices PART TEMP RANGE MP3 Players PACKAGE MARK Cameras Instrumentation M AX3421E E H J+ -40 C to +85 C 32 TQFP M AX3421E E TJ+ -40 C to +85 C 32 TQFN- E P *BTBG *EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maximintegrated.com. 19-3953 Rev 4 7/13MAX3421E USB Peripheral/Host Controller with SPI Interface Features in Host Operation Features in Peripheral Operation Eleven Registers (R21R31) are Added to the Built-In Endpoint FIFOS MAX3420E Register Set to Control Host Operation EP0: CONTROL (64 bytes) EP1: OUT, BULK or INTERRUPT, 2 x 64 Bytes Host Controller Operates at Full Speed or Low (Double-Buffered) Speed EP2: IN, BULK or INTERRUPT, 2 x 64 Bytes FIFOS (Double-Buffered) SNDFIFO: Send FIFO, Double-Buffered 64-Byte EP3: IN, BULK or INTERRUPT (64 Bytes) RCVFIFO: Receive FIFO, Double-Buffered 64-Byte Double-Buffered Data Endpoints Increase Handles DATA0/DATA1 Toggle Generation and Throughput by Allowing the SPI Master to Checking Transfer Data Concurrent with USB Transfers Performs Error Checking for All Transfers SETUP Data Has its Own 8-Byte FIFO, Simplifying Automatically Generates SOF (Full-Speed)/EOP Firmware (Low-Speed) at 1ms Intervals Automatically Synchronizes Host Transfers with Typical Application Circuits Beginning of Frame (SOF/EOP) 3.3V Reports Results of Host Requests REGULATOR Supports USB Hubs SPI Supports ISOCHRONOUS Transfers 3, 4 USB MAX3421E P Simple Programming INT SIE Automatically Generates Periodic SOF (Full-Speed) or EOP (Low-Speed) Frame Markers SPI Master Loads Data, Sets Function Address, Figure 1. The MAX3421E Connects to Any Microprocessor Endpoint, and Transfer Type, and Initiates the Using 3 or 4 Interface Pins Transfer MAX3421E Responds with an Interrupt and The MAX3421E connects to any microprocessor (P) Result Code Indicating Peripheral Response using 3 or 4 interface pins (Figure 1). On a simple Transfer Request Can be Loaded Any Time microprocessor without SPI hardware, these can be SIE Synchronizes with Frame Markers bit-banged general-purpose I/O pins. Eight GPIN and For Multipacket Transfers, the SIE eight GPOUT pins on the MAX3421E more than Automatically Maintains and Checks the replace the P pins necessary to implement the inter- Data Toggles face. Although the MAX3421E SPI hardware includes separate data-in (MOSI, master-out, slave-in) and data- out (MISO, master-in, slave-out) pins, the SPI interface can also be configured for the MOSI pin to carry bidi- rectional data, saving an interface pin. This is referred to as half-duplex mode. 2 Maxim Integrated