AS3001204-0054X0PSAR Avalanche Technology

1Mbit 16Mbit SPI (4-4-4) P-SRAM Memory High Performance Serial Persistent SRAM Memory (AS1001204, AS1004204, AS1008204, AS1016204, AS3001204, AS3004204, AS3008204, AS3016204) Features Interface Packages Serial Peripheral Interface QSPI (4-4-4) 8-pad WSON (5.0mm x 6.0mm) Single Data Rate Mode: 108MHz 8-pin SOIC (5.2mm x 5.2mm) Double Data Rate Mode: 54MHz 24-ball FBGA (6.0mm x 8.0mm) Technology Data Protection 40nm pMTJ STT-MRAM Hardware Based Virtually unlimited Endurance and Data Write Protect Pin (WP ) Retention (see Endurance and Data Software Based Retention specification on page 48) Address Range Selectable through Density Configuration bits (Top/Bottom, Block Protect 2:0 ) 1Mb, 4Mb, 8Mb, 16Mb Operating Voltage Range Identification 64-bit Unique ID VCC: 1.71V 2.00V 64-bit User Programmable Serial Number V : 2.70V 3.60V CC Operating Temperature Range Augmented Storage Array 256-byte User Programmable with Write Industrial: -40C to 85C Industrial Plus: -40C to 105C Protection Supports JEDEC Reset RoHS & REACH Compliant Performance Device Operation Typical Values Units Frequency of Operation 108 (maximum) MHz Standby Current 160 (typical) A Deep Power Down Current 5 (typical) A Hibernate Current 0.1 (typical) A Active Read Current (4-4-4) SDR 108MHz 19 (typical) mA Active Write Current (4-4-4) SDR 108MHz 38 (typical) mA R e v i s i o n : O A v a l a n c h e T e c h n o l o g y P a g e 1 62 1Mbit 16Mbit SPI (4-4-4) P-SRAM Memory Table of Contents Features ...................................................................................................................................................... 1 Performance .............................................................................................................................................. 1 Table of Contents ..................................................................................................................................... 2 General Description ................................................................................................................................. 4 Ordering Options ..................................................................................................................................... 5 Valid Combinations Standard ...................................................................................................... 5 Signal Description and Assignment ................................................................................................. 10 Package Options .................................................................................................................................... 12 8-Pad WSON (Top View) ................................................................................................................... 12 8-Pin SOIC (Top View) ....................................................................................................................... 12 24-Ball FBGA (Top View) .................................................................................................................. 12 Package Drawings ................................................................................................................................. 13 8-Pad WSON ........................................................................................................................................ 13 8-Pin SOIC ............................................................................................................................................ 14 24-Ball FBGA ....................................................................................................................................... 15 Architecture ............................................................................................................................................. 16 Device Initialization ............................................................................................................................... 19 Memory Map ............................................................................................................................................ 21 Augmented Storage Array Map .......................................................................................................... 21 Register Addresses ............................................................................................................................... 22 Register Map ........................................................................................................................................... 23 Status Register / Device Protection Register (Read/Write) ........................................................... 23 Augmented Storage Array Protection Register (Read/Write) ........................................................ 24 Device Identification Register (Read Only) ...................................................................................... 25 Serial Number Register (Read/Write) ............................................................................................... 26 Unique Identification Register (Read Only) ...................................................................................... 26 Configuration Register 1 (Read/Write) .............................................................................................. 27 Configuration Register 2 (Read/Write) .............................................................................................. 27 Configuration Register 3 (Read/Write) .............................................................................................. 29 R e v i s i o n : O A v a l a n c h e T e c h n o l o g y P a g e 2 62