Version 1.4 2010 Features PEX 8615 General Features o 12-lane PCI Express switch PEX 8615 - Integrated 5.0 GT/s SerDes o Up to 12 configurable ports 2 o 19 x 19mm , 324-ball HSBGA o Typical Power: 1.79 Watts PEX 8615 Key Features Flexible & Versatile 12-lane 12-port PCI Express Switch o Standards Compliant - PCI Express Base Specification r2.0 (Backwards compatible with PCIe The ExpressLane PEX 8615 device offers PCI Express switching capability r1.0a/1.1) enabling users to add scalable high bandwidth non-blocking interconnection to a - PCI Power Management Spec r1.2 wide variety of applications including control planes, communication platforms, - Microsoft Vista Compliant servers, storage systems and embedded systems. The PEX 8615 is well suited for - Supports Access Control Services fan-out, aggregation, peer-to-peer, and intelligent I/O module applications. - Dynamic link-width control o Integrated DMA Engine Low Packet Latency & High Performance - Four DMA Channels The PEX 8615 architecture supports packet cut-thru with a maximum latency of - Internal Descriptor Support - DMA function independent from 140ns. This, combined with large packet memory and non-blocking internal switch transparent switch function architecture, provides full line rate on all ports for low-latency applications such as - 64-bit Addressing communications and servers. The low latency enables applications to achieve high - Prefetch Descriptor Mode throughput and performance. In addition to low latency, the device supports a max - Up to 4.0 GB/s throughput per channel payload size of 2048 bytes, enabling the user to achieve even higher throughout. o Dual-Host & Fail-Over Support - Configurable Non-Transparent port Integrated DMA Engine (NTB) The PEX 8615 provides a versatile and powerful DMA engine built in to the device - Moveable upstream port which can be used as a stand alone DMA engine. The DMA engine removes the - Crosslink port capability burden resulting from having to move data between devices away from the o High Performance processor. This allows the processor to perform computational tasks instead. The - Cut-Thru latency: 140ns four DMA channels can support high data rate transfers between IO devices - 2KB max payload size - Read Pacing connected to any of the available ports in the PEX8615. Additionally, the DMA - Dual-Cast engine in the PEX 8615 can be used to complement the DMA engine in the o Flexible Configuration processor by providing additional DMA channels for higher performance. - 12 flexible & configurable ports (x1 or x4) - Configurable with strapping pins, Data Integrity 2 EEPROM, I C, or Host software The PEX 8615 provides end-to-end CRC protection (ECRC) and Poison bit support - Lane and polarity reversal to enable designs that require guaranteed error-free packets. PLX also supports o PCI Express Power Management data path parity and memory (RAM) error correction as packets pass through the - Link power management states: L0, L0s, switch. L1, L2/L3 Ready, and L3 - Device states: D0 and D3 hot Dual-Host and Fail-Over Support o Spread Spectrum Clock Isolation The PEX 8615 supports full non-transparent bridging (NTB) functionality to allow - Dual clock domain implementation of multi-host systems and intelligent I/O modules in applications o Quality of Service (QoS) which require redundancy support such as communications, storage, and servers. - Two Virtual Channels (VC) per port - Eight Traffic Classes per port Non-transparent bridges allow systems to isolate host memory domains by - Weighted Round-Robin Port & VC presenting the processor subsystem as an endpoint rather than another memory Arbitration system. Base address registers are used to translate addresses doorbell registers are o Reliability, Availability, Serviceability 2 used to send interrupts between the address domains and scratchpad registers are - All ports Hot-Plug capable thru I C (Hot-Plug Controller on every port) accessible from both address domains to allow inter-processor communication. - Data path protection Interoperability - Memory (RAM) error correction - Port Status bits and GPIO available The PEX 8615 is designed to be fully compliant with the PCI Express Base - Per port error diagnostics Specification r2.0 and is backwards compatible to PCI Express Base Specification - Performance monitoring r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and (per port payload & header counters) polarity reversal. Furthermore, the PEX 8615 is designed for Microsoft Vista compliance. All PLX switches undergo thorough interoperability testing in PLXs Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure compatibility with PCI Express devices in the market. off, low, typical, and high. The SerDes block also supports Flexible Port Configurations loop-back modes and advanced reporting of error The PEX 8615 supports a large number of port configurations conditions, which enables efficient debug and management of as shown in figure 1 below. Please refer to the PEX 8615 the entire system. datasheet for more port configuration options. Port and Virtual Channel (VC) Arbitration The PEX 8615 switch supports hardware fixed and Weighted Round-Robin Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers for better system performance. The PEX 8615 also supports WRR VC arbitration scheme between the two virtual channels. Applications Suitable for fan-out, control plane applications, embedded systems as well as intelligent I/O applications, PEX 8615 can be configured for a wide variety of form factors and applications. Figure 1. PEX8615 Port Configurations Fan-Out The PEX 8615 switch, with its high port count and flexible configurations, allows user specific tuning to a variety of host- Hot-Plug for High Availability centric as well as peer-to-peer applications. Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8615 Hot-Plug capability feature makes it suitable for High Availability (HA) applications. If the PEX 8615 is used in an application where one or more of its downstream ports connect to PCI Express slots, each ports Hot-Plug Controller can be used to manage the Hot-Plug event of its associated slot. Every port on the PEX 8615 is equipped with a Hot-Plug control/status register to support Hot-Plug 2 capability through external logic via the I C interface. Dual Cast The PEX 8615 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in storage, security, and mirroring applications. Read Pacing Figure 2. Fan-in/out Usage The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. In the case Figure 2 shows a typical fan-out design, where the processor where a downstream device requests several long reads back- provides a PCI Express link that needs to be fanned into a to-back, the Root Complex gets tied up in serving this larger number of smaller ports for a variety of I/O functions, downstream port. If this port has a narrow link and is therefore each with different bandwidth requirements. slow in receiving these read packets from the Root Complex, In this example, the PEX 8615 would typically have a 1-lane then other downstream ports may become starved thus, upstream port, and as many as 11 downstream ports. The impacting performance. The Read Pacing feature enhances downstream ports provide x1 PCI Express connectivity to the performances by allowing for the adequate servicing of all endpoints. With its twelve ports, the PEX 8615 can provide downstream devices by intelligent handling of read requests. fan-out connectivity to up to eleven PCI Express devices. The figure also shows how some of the ports can be bridged to SerDes Power and Signal Management provide PCI slots or Generic devices through the use of the The PEX 8615 provides low power capability that is fully PEX 8311 and PEX 8112 PCIe bridging devices. compliant with the PCI Express power management specification. In addition, the SerDes physical links can be Control Plane Application turned off when unused for even lower power. The PEX 8615 The PEX 8615 is ideal for control planes in routers and other supports software control of the SerDes outputs to allow communications sub-systems to meet increased packet optimization of power and signal strength in a system. The processing needs without compromising latency. Figure 3 PLX SerDes implementation supports four levels of power