PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports Highlights The ExpressLane PEX 8747 device offers Multi-Host PCI Express switching capability enabling users to connect a host to its respective PEX 8747 General Features o 48-lane, 5-port PCIe Gen 3 switch endpoints via scalable, high bandwidth, non-blocking interconnection - Integrated 8.0 GT/s SerDes 2 to a variety of graphics applications. The PEX 8747 is optimized to o 27 x 27mm , 676-pin FCBGA package o Typical Power: 8.0 Watts support high-resolution graphics while supporting peer-to-peer traffic and multicast for maximum performance. PEX 8747 Key Features o Standards Compliant High Performance & Low Packet Latency - PCI Express Base Specification, r3.0 The PEX 8747 architecture supports packet cut-thru with a maximum (compatible w/ PCIe r1.0a/1.1 & 2.0) latency of 100ns (x16 to x16). This, combined with large packet memory, - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant flexible common buffer/FC credit pool and non-blocking internal switch - Supports Access Control Services architecture, provides full line rate on all ports for performance-hungry - Dynamic link-width control applications such as servers and switch fabrics. The low latency enables - Dynamic SerDes speed control applications to achieve high throughput and performance. In addition to low o High Performance latency, the device supports a packet payload size of up to 2048 bytes, performancePAK 9 Read Pacing (bandwidth throttling) enabling the user to achieve even higher throughput. 9 Multicast 9 Dynamic Buffer/FC Credit Pool Data Integrity - Non-blocking switch fabric The PEX 8747 provides end-to-end CRC (ECRC) protection and Poison bit - Full line rate on all ports - Packet Cut-Thru with 100ns max packet support to enable designs that require end-to-end data integrity. PLX also latency (x16 to x16) supports data path parity and memory (RAM) error correction circuitry - 2KB Max Payload Size throughout the internal data paths as packets pass through the switch. o Flexible Configuration - Ports configurable as x8 or x16 Flexible Configuration - Registers configurable with strapping x16 x16 2 pins, EEPROM, I C, or host software The PEX 8747s 5 ports can be - Lane and polarity reversal configured to lane widths of x8 or - Compatible with PCIe 1.0a PM x16. Flexible buffer allocation, PEX 8747 PEX 8747 o Quality of Service (QoS) along with the device s flexible - Eight traffic classes per port packet flow control, maximizes - Weighted round-robin source port arbitration throughput for applications where x16 x16 x16 x8 x8 o Reliability, Availability, Serviceability more traffic flows in the visionPAK x16 downstream, rather than 9 Per Port Performance Monitoring upstream, direction. Any port can Per port payload & header counters be designated as the upstream 9 SerDes Eye Capture PEX 8747 9 PCIe Packet Generator port, which can be changed 9 Error Injection and Loopback dynamically. Figure 1 shows 2 - All ports hot plug capable thru I C some of the PEX 8747s common (Hot Plug Controller on every port) x8 x8 x8 x8 port configurations. - ECRC and Poison bit support Figure 1. Common Port Configurations - Data Path parity - Memory (RAM) Error Correction SerDes Power and Signal Management - INTA and FATAL ERR signals The PEX 8747 provides low power capability that is fully compliant with the - Advanced Error Reporting PCIe power management specification and supports software control of the - Port Status bits and GPIO available Per port error diagnostics SerDes outputs to allow optimization of power and signal strength in a - JTAG AC/DC boundary scan system. Furthermore, the SerDes block supports loop-back modes and advanced reporting of error conditions, which enables efficient management of the entire system. PLX Technology, www.plxtech.com Page 1 of 4 10/20/2010, Version 1.0 PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports remain in the common buffer pool and can then be used Interoperability for faster FC credit updates. The PEX 8747 is designed to be fully compliant with the PCI Express Base Specification r2.0, and is backwards compatible to PCI Express Base Specification r1.1 and visionPAK Another PLX exclusive, visionPAK is a debug diagnostics r1.0a. Additionally, it supports auto-negotiation, lane suite of integrated hardware and software instruments that reversal, and polarity reversal. Furthermore, the PEX 8747 is tested for Microsoft Vista compliance. All PLX users can use to help bring their systems to market faster. visionPAK features consist of Performance Monitoring, switches undergo thorough interoperability testing in SerDes Eye Capture, Error Injection, SerDes Loopback, PLXs Interoperability Lab and compliance testing at the PCI-SIG plug-fest. and more. Performance Monitoring performancePAK The PEX 8747s real time performance monitoring allows Exclusive to PLX, performancePAK is a suite of unique users to literally see ingress and egress performance on and innovative performance features which allows PLXs each port as traffic passes through the switch using PLXs Gen 2 switches to be the highest performing Gen 2 Software Development Kit (SDK). The monitoring is switches in the market today. The performancePAK completely passive and therefore has no affect on overall features consists of the Read Pacing, Multicast, and system performance. Internal counters provide extensive Dynamic Buffer Pool. granularity down to traffic & packet type and even allows for the filtering of traffic (i.e. count only Memory Writes). Read Pacing The Read Pacing feature allows users to throttle the SerDes Eye Capture amount of read requests being made by downstream Users can evaluate their systems signal integrity at the devices. When a downstream device requests several long physical layer using the PEX 8747s SerDes Eye Capture reads back-to-back, the Root Complex gets tied up in feature. Using PLXs SDK, users can view the receiver serving that downstream port. If that port has a narrow link eye of any lane on the switch. Users can then modify and is therefore slow in receiving these read packets from SerDes settings and see the impact on the receiver eye. the Root Complex, then other downstream ports may Figure 2 shows a screenshot of the SerDes Eye Capture become starved thus, impacting performance. The Read feature in the SDK. Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. Multicast The Multicast feature enables the copying of data (packets) from one ingress port to multiple (up to 4) egress ports in one transaction allowing for higher performance in dual- graphics, storage, security, and redundant applications, among others. Multicast relieves the CPU from having to conduct multiple redundant transactions, resulting in higher system performance. Dynamic Buffer Pool The PEX 8747 employs a dynamic buffer pool for Flow Control (FC) management. As opposed to a static buffer Figure 2. SerDes Eye Capture scheme which assigns fixed, static buffers to each port, PLXs dynamic buffer allocation scheme utilizes a PCIe Packet Generator common pool of FC Credits which are shared by other The PEX 8747 features a full-fledged PCIe Packet ports. This shared buffer pool is fully programmable by the Generator capable of creating programmable PCIe traffic user, so FC credits can be allocated among the ports as running at up to Gen 3 speeds and capable of saturating a needed. Not only does this prevent wasted buffers and x16 link. Using PLXs Software Development Kit inappropriate buffer assignments, any unallocated buffers (www.plxtech.com/sdk), designers can create custom PLX Technology, www.plxtech.com Page 2 of 4 10/20/2010, Version 1.0