PEX8796, PCI Express Gen3 Switch, 96 Lanes, 24 Ports TM Highlights The ExpressLane PEX8796 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX8796 General Features respective endpoints via scalable, high bandwidth, non-blocking o 96-lane, 24-port PCIe Gen3 switch Integrated 8.0 GT/s SerDes interconnection to a wide variety of applications including servers, storage 2 o 35 x 35mm , 1156-ball FCBGA package systems, and communications platforms. The PEX8796 is well suited for o Typical Power: 18.6 Watts fan-out, aggregation, and peer-to-peer applications. PEX8796 Key Features Multi-Host Architecture o Standards Compliant The PEX8796 employs an enhanced architecture, which allows users to PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0) configure the device in legacy single-host mode or multi-host mode with up PCI Power Management Spec, r1.2 to four host ports capable of 1+1 (one active & one backup) or N+1 (N active Microsoft Windows Logo Compliant & one backup) host failover. This powerful architectural enhancement Supports Access Control Services enables users to build PCIe based systems to support high-availability, Dynamic link-width control failover, redundant and clustered systems. Dynamic SerDes speed control o High Performance High Performance & Low Packet Latency performancePAK The PEX8796 architecture supports packet cut-thru with a maximum Multicast Dynamic Buffer/FC Credit Pool latency of 150ns (x16 to x16). This, combined with large packet memory, Non-blocking switch fabric flexible common buffer/FC credit pool and non-blocking internal switch Full line rate on all ports architecture, provides full line rate on all ports for performance-hungry Cut-Thru with 150ns max packet latency applications such as servers and switch fabrics. The low latency enables 2KB Max Payload Size o Multi-Host & Fail-Over Support applications to achieve high throughput and performance. In addition to low 2 Configurable Non-Transparent ports latency, the device supports a packet payload size of up to 2048 bytes, Failover with Non-Transparent port enabling the user to achieve even higher throughput. Up to 4 upstream/Host ports with 1+1 or N+1 failover to other upstream ports Data Integrity o Quality of Service (QoS) The PEX8796 provides end-to-end CRC (ECRC) protection and Poison bit Traffic Class Queuing support to enable designs that require end-to-end data integrity. PLX also Eight traffic classes per port Weighted round-robin source supports data path parity and memory (RAM) error correction circuitry port arbitration throughout the internal data paths as packets pass through the switch. o Reliability, Availability, Serviceability visionPAK Flexible Configuration Per Port Performance Monitoring The PEX8796s 24 ports can be configured to lane SerDes Eye Capture widths of x4, x8, or x16. Flexible buffer allocation, PCIe Packet Generator along with the device s flexible packet flow Error Injection and Loopback control, maximizes throughput for applications 6 Hot-Plug port with native HP Signals 2 All ports Hot-Plug capable thru I C where more traffic flows in the downstream, rather SSC Isolation on up to 24 ports than upstream, direction. Any port can be ECRC and Poison bit support designated as the upstream port, which can be Data Path parity changed dynamically. Figure 1 shows some of the Memory (RAM) Error Correction Advanced Error Reporting PEX8796s common port configurations in legacy Port Status bits and GPIO available Single-Host mode. JTAG AC/DC boundary scan The PEX8796 can also be configured in Multi-Host mode where users can choose up to four ports as host/upstream ports and assign a desired number of downstream ports to each host. In Multi-Host mode, a virtual switch is created for each host port and its associated downstream ports inside the device. The traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. Figure 2 illustrates some configurations of the PEX8796 in Multi-Host mode where each ellipse represents a virtual switch inside the device. PLX Technology, www.plxtech.com Page 1 of 5 24July12 v1.2 PEX8796, PCI Express Gen3 Switch, 96 Lanes, 24 Ports The PEX8796 also Host 1 Host 2 Host 1 Host 2 provides several ways to PEX 8796 PEX 8796 configure its registers. The device can be End End End End End End End End configured through Point Point Point Point Point Point Point Point 2 Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over strapping pins, I C interface, host software, Hot-Plug for High Availability or an optional serial Hot plug capability allows users to replace hardware EEPROM. This allows modules and perform maintenance without powering for easy debug during down the system. The PEX8796 Hot-Plug capability the development phase, feature makes it suitable for High Availability (HA) performance monitoring applications. Four downstream ports include a Standard during the operation Hot Plug Controller. If the PEX8796 is used in an phase, and driver or software upgrade. application where one or more of its downstream ports connect to PCI Express slots, each ports Hot-Plug Dual-Host & Failover Support Controller can be used to manage the Hot-Plug event of In Single-Host mode, the PEX8796 supports a Non- its associated slot. Every port on the PEX8796 is Transparent (NT) Port, which enables the equipped with a Hot-Plug control/status register to implementation of dual-host systems for redundancy support Hot-Plug capability through external logic via and host failover 2 the I C interface. capability. The NT port allows systems to isolate SerDes Power and Signal Management host memory domains by The PEX8796 supports software control of the SerDes presenting the processor outputs to allow optimization of power and signal subsystem as an endpoint strength in a system. The PLX SerDes implementation rather than another supports four levels of power off, low, typical, and memory system. Base high. The SerDes block also supports loop-back modes address registers are used and advanced reporting of error conditions, which to translate addresses enables efficient management of the entire system. doorbell registers are used to send interrupts between Interoperability the address domains and The PEX8796 is designed to be fully compliant with the scratchpad registers (accessible by both CPUs) allow PCI Express Base Specification r3.0, and is backwards inter-processor communication (see Figure 3). compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally, it supports auto-negotiation, lane Multi-Host & Failover Support reversal, and polarity reversal. Furthermore, the In Multi-Host mode, PEX8796 can be configured with PEX8796 is tested for Microsoft Windows Logo up to four upstream host ports, each with its own compliance. All PLX switches undergo thorough dedicated downstream ports. The device can be interoperability testing in PLXs Interoperability Lab configured for 1+1 redundancy or N+1 redundancy. The and compliance testing at the PCI-SIG plug-fest. PEX8796 allows the hosts to communicate their status to each other via special door-bell registers. In failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. Figure 4a shows a two host system in Multi- Host mode with two virtual switches inside the device and Figure 4b shows Host 1 disabled after failure and Host 2 having taken over all of Host 1s end-points. PLX Technology, www.plxtech.com Page 2 of 5 24July12 v1.2