WM8152 Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output DESCRIPTION FEATURES 16-bit ADC The WM8152 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals 12MSPS conversion rate from CCD sensors or Contact Image Sensors (CIS) at pixel Low power - 225mW typical sample rates of up to 12MSPS. 5V single supply or 5V/3.3V dual supply operation The device includes a complete analogue signal processing Single channel operation channel containing Reset Level Clamping, Correlated Correlated double sampling Double Sampling, Programmable Gain and Offset adjust Programmable gain (8-bit resolution) functions. Internal multiplexers allow fast switching of offset Programmable offset adjust (8-bit resolution) and gain for line-by-line colour processing. The output from Programmable clamp voltage this channel is time multiplexed into a high-speed 16-bit Analogue to Digital Converter. The digital output data is 4-bit wide multiplexed data output format available in 4-bit wide multiplexed format. Internally generated voltage references 20-lead SSOP package An internal 4-bit DAC is supplied for internal reference level generation. This may be used to reference CIS signals or Serial control interface during Reset Level Clamping to clamp CCD signals. An APPLICATIONS external reference level may also be supplied. ADC references are generated internally, ensuring optimum Flatbed and sheetfeed scanners performance from the device. USB compatible scanners Using an analogue supply voltage of 5V, a digital core Multi-function peripherals voltage of 5V, and a digital interface supply of either 5V or High-performance CCD sensor interface 3.3V, the WM8152 typically only consumes 225mW when operating from a single 5V supply. BLOCK DIAGRAM VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB VREF/BIAS CL R V TIMING CONTROL S S R 8 M OFFSET G U DAC X B OP 0 16- DATA OP 1 VINP RLC CDS + PGA + BIT I/O OP 2 ADC PORT I/P SIGNAL OP 3 /SDO 8 POLARITY VRLC/VBIAS ADJUST R M G U X B W WM8152 CONFIGURABLE SEN 4 RLC SERIAL SCK DAC CONTROL SDI INTERFACE AGND1 AGND2 DGND Rev 4.4 Copyright Cirrus Logic, Inc., 2002 2020 JAN 2020 WM8152 TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS .............................................................................................................. 1 BLOCK DIAGRAM ......................................................................................................... 1 TABLE OF CONTENTS .................................................................................................. 2 PIN CONFIGURATION ................................................................................................... 3 ORDERING INFORMATION ........................................................................................... 3 PIN DESCRIPTION ......................................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ................................................................................. 5 RECOMMENDED OPERATING CONDITIONS .............................................................. 6 THERMAL PERFORMANCE .......................................................................................... 6 ELECTRICAL CHARACTERISTICS .............................................................................. 7 INPUT VIDEO SAMPLING ......................................................................................................... 9 OUTPUT DATA TIMING ........................................................................................................... 10 SERIAL INTERFACE ............................................................................................................... 11 INTERNAL POWER ON RESET CIRCUIT ................................................................... 12 DEVICE DESCRIPTION ............................................................................................... 14 INTRODUCTION ...................................................................................................................... 14 INPUT SAMPLING ................................................................................................................... 14 RESET LEVEL CLAMPING (RLC) ........................................................................................... 14 CDS/NON-CDS PROCESSING ............................................................................................... 16 OFFSET ADJUST AND PROGRAMMABLE GAIN .................................................................. 16 ADC INPUT BLOACK LEVEL ADJUST ................................................................................... 17 OVERALL SIGNAL FLOW SUMMARY .................................................................................... 17 CALCULATING OUTPUT FOR ANY GIVEN INPUT ................................................................ 18 OUTPUT DATA FORMAT ........................................................................................................ 19 CONTROL INTERFACE ........................................................................................................... 20 TIMING REQUIREMENTS ....................................................................................................... 21 PROGRAMMABLE VSMP DETECT CIRCUIT ......................................................................... 21 REFERENCES ......................................................................................................................... 22 POWER SUPPLY ..................................................................................................................... 22 POWER MANAGEMENT ......................................................................................................... 22 OPERATING MODES .............................................................................................................. 22 OPERATING MODE TIMING DIAGRAMS ............................................................................... 23 DEVICE CONFIGURATION .......................................................................................... 25 REGISTER MAP ...................................................................................................................... 25 REGISTER MAP DESCRIPTION ............................................................................................. 26 APPLICATIONS INFORMATION ................................................................................. 28 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 28 RECOMMENDED EXTERNAL COMPONENTS VALUES ....................................................... 29 PACKAGE DIMENSIONS ............................................................................................. 30 IMPORTANT NOTICE .................................................................................................. 31 REVISION HISTORY .................................................................................................... 32 2 Rev 4.4