Critical Link, LLC MitySOM www.criticallink.com MitySOM-1808F Processor Card 5-MAR-2014 FEATURES TI AM1808 ARM9 Application Processor - 456 MHz ARM926EJ-S MPU 16 KB L1 Program Cache 16 KB L1 Data Cache 8 KB Internal RAM 64 KB boot ROM JTAG Emulation/Debug On-Board Xilinx Spartan-6 FPGA - Up To XC6SLX45 Up To 2,088 KBits Block RAM Up To 6,822 Slices (6 Input LUTs) - 1050 Mbps data rate - JTAG Interface/Debug APPLICATIONS Embedded Instrumentation Up To 256 MB mDDR2 CPU RAM Industrial Automation Up To 512 MB Parallel NAND FLASH Industrial Instrumentation 8 MB SPI based NOR FLASH Medical Instrumentation Integrated Power Management Embedded Control Processing Standard SO-DIMM-200 Interface Network Enabled Data Acquisition - 96 FPGA User I/O Pins Test and Measurement - 10/100 EMAC MII / MDIO Software Defined Radio - 2 UARTS Bar Code Scanners - 2 McBSPs Power Protection Systems - 2 USB Ports Portable Data Terminals - Video Output - Camera/Video Input BENEFITS - MMC/SD Rapid Development / Deployment - SATA Multiple Connectivity and Interface Options - Single 3.3V Power Supply Rich User Interfaces High System Integration High Level OS Support - Linux - QNX 6.4 - Windows Embedded CE Ready - ThreadX Real Time OS DESCRIPTION The MitySOM-1808F is a highly configurable, very small form-factor processor card that features a Texas Instruments AM1808 456 MHz ARM Applications Processor tightly integrated with the Xilinx Spartan-6 Field Programmable Gate Array (FPGA), FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The design of the MitySOM-1808F allows end users the capability to develop programs/logic images for both the ARM processor and the FGPA. The MitySOM-1808F provides a complete and flexible digital processing infrastructure necessary for the most demanding embedded applications development. 1 Copyright 2012, Critical Link LLC Specifications Subject to Change Critical Link, LLC MitySOM www.criticallink.com MitySOM-1808F Processor Card 5-MAR-2014 The AM1808 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich software applications programmer interfaces (APIs) expected by modern system designers. The ARM architecture supports several operating systems, including Linux, QNX and Windows XP embedded. 1.2V 8MB NOR Flash Up To 512MB Up To 256MB (SPI interface) NAND Flash 1.8V mDDR Memory Power For uBoot 8-bit wide 2.5V 16-bit wide Management bootloader For root FFS 3.3V EMIFA (16-bit) System JTAG Clocks JTAG JTAG/Emulator Header Emulator Header MMCSD 1 Xilinx Texas Instruments EMAC RMII Spartan-6 AM1808 UHPI FPGA 456-MHz ARM926EJ-S RISC MPU uPP Up To XC6SLX45 LCD (Many pins are multiplexed between peripherals) CSG324 pkg. VPIF I/O Boot Config FPGA I/O Banks can be 1.8V, 2.5V, or 3.3V SO-DIMM-200 (DDR2 Connector) Figure 1 MitySOM-1808F Block Diagram Figure 1 provides a top level block diagram of the MitySOM-1808F processor card. As shown in the figure, the primary interface to the MitySOM-1808F is through a standard SO-DIMM-200 card edge interface. The interface provides power, synchronous serial connectivity, and up to 96 pins of configurable FPGA I/O for application defined interfacing. Details of the SO-DIMM-200 connector interface are included in the SO- DIMM-200 Interface Description, below. FPGA Bank I/O The MitySOM-1808F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA. These I/O lines and their associated logic are completely configurable within the FPGA at the end users discretion. With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled banks may be configured to operate on a different electrical interface standard based on 2 Copyright 2012, Critical Link LLC Specifications Subject to Change EMAC MII/MDIO MMCSD 0 UART 0,1,2 McBSP 0,1 SPI 0,1 I2C 0,1 McASP eCAP eHRPWM Timers SATA USB 0,1 Resets & RTC Boot Config I/O Bank Power Programmable I/O I/O Bank Power Programmable I/O 3.3 V GND