Sample & Support & Reference Product Tools & Technical Community Buy Design Folder Documents Software AM3359, AM3358, AM3357, AM3356, AM3354, AM3352 SPRS717HOCTOBER 2011REVISED MAY 2015 AM335x Sitara Processors 1 Device Overview 1.1 Features 1 Supports Protocols such as EtherCAT , Up to 1-GHz Sitara ARM Cortex -A8 32 Bit PROFIBUS, PROFINET, EtherNet/IP, and RISC Processor More NEON SIMD Coprocessor Two Programmable Real-Time Units (PRUs) 32KB of L1 Instruction and 32KB of Data Cache 32-Bit Load/Store RISC Processor Capable With Single-Error Detection (Parity) of Running at 200 MHz 256KB of L2 Cache With Error Correcting Code 8KB of Instruction RAM With Single-Error (ECC) Detection (Parity) 176KB of On-Chip Boot ROM 8KB of Data RAM With Single-Error 64KB of Dedicated RAM Detection (Parity) Emulation and Debug - JTAG Single-Cycle 32-Bit Multiplier With 64-Bit Interrupt Controller (up to 128 Interrupt Accumulator Requests) Enhanced GPIO Module Provides Shift- On-Chip Memory (Shared L3 RAM) In/Out Support and Parallel Latch on 64KB of General-Purpose On-Chip Memory External Signal Controller (OCMC) RAM 12KB of Shared RAM With Single-Error Accessible to All Masters Detection (Parity) Supports Retention for Fast Wakeup Three 120-Byte Register Banks Accessible by External Memory Interfaces (EMIF) Each PRU mDDR(LPDDR), DDR2, DDR3, DDR3L Interrupt Controller Module (INTC) for Handling Controller: System Input Events mDDR: 200-MHz Clock (400-MHz Data Local Interconnect Bus for Connecting Internal Rate) and External Masters to the Resources Inside DDR2: 266-MHz Clock (532-MHz Data Rate) the PRU-ICSS DDR3: 400-MHz Clock (800-MHz Data Rate) Peripherals Inside the PRU-ICSS: DDR3L: 400-MHz Clock (800-MHz Data One UART Port With Flow Control Pins, Rate) Supports up to 12 Mbps 16-Bit Data Bus One Enhanced Capture (eCAP) Module 1GB of Total Addressable Space Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT Supports One x16 or Two x8 Memory Device Configurations One MDIO Port General-Purpose Memory Controller (GPMC) Power, Reset, and Clock Management (PRCM) Module Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Controls the Entry and Exit of Stand-By and Selects (NAND, NOR, Muxed-NOR, SRAM) Deep-Sleep Modes Uses BCH Code to Support 4-, 8-, or 16-Bit Responsible for Sleep Sequencing, Power ECC Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Uses Hamming Code to Support 1-Bit ECC Sequencing Error Locator Module (ELM) Clocks Used in Conjunction With the GPMC to Integrated 15- to 35-MHz High-Frequency Locate Addresses of Data Errors from Oscillator Used to Generate a Reference Syndrome Polynomials Generated Using a Clock for Various System and Peripheral BCH Algorithm Clocks Supports 4-, 8-, and 16-Bit per 512-Byte Supports Individual Clock Enable and Block Error Location Based on BCH Disable Control for Subsystems and Algorithms Peripherals to Facilitate Reduced Power Programmable Real-Time Unit Subsystem and Consumption Industrial Communication Subsystem (PRU-ICSS) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.AM3359, AM3358, AM3357, AM3356, AM3354, AM3352 SPRS717HOCTOBER 2011REVISED MAY 2015 www.ti.com Five ADPLLs to Generate System Clocks Transmission (SPDIF, IEC60958-1, and (MPU Subsystem, DDR Interface, USB and AES-3 Formats) 2 Peripherals MMC and SD, UART, SPI, I C , FIFO Buffers for Transmit and Receive (256 L3, L4, Ethernet, GFX SGX530 , LCD Pixel Bytes) Clock) Up to Six UARTs Power All UARTs Support IrDA and CIR Modes Two Nonswitchable Power Domains (Real- All UARTs Support RTS and CTS Flow Time Clock RTC , Wake-Up Logic Control WAKEUP ) UART1 Supports Full Modem Control Three Switchable Power Domains (MPU Up to Two Master and Slave McSPI Serial Subsystem MPU , SGX530 GFX , Interfaces Peripherals and Infrastructure PER ) Up to Two Chip Selects Implements SmartReflex Class 2B for Up to 48 MHz Core Voltage Scaling Based On Die Up to Three MMC, SD, SDIO Ports Temperature, Process Variation, and 1-, 4- and 8-Bit MMC, SD, SDIO Modes Performance (Adaptive Voltage Scaling AVS ) MMCSD0 has Dedicated Power Rail for Dynamic Voltage Frequency Scaling (DVFS) 1.8 V or 3.3-V Operation Real-Time Clock (RTC) Up to 48-MHz Data Transfer Rate Real-Time Date (Day-Month-Year-Day of Week) Supports Card Detect and Write Protect and Time (Hours-Minutes-Seconds) Information Complies With MMC4.3, SD, SDIO 2.0 Internal 32.768-kHz Oscillator, RTC Logic and Specifications 2 1.1-V Internal LDO Up to Three I C Master and Slave Interfaces Independent Power-on-Reset Standard Mode (up to 100 kHz) (RTC PWRONRSTn) Input Fast Mode (up to 400 kHz) Dedicated Input Pin (EXT WAKEUP) for Up to Four Banks of General-Purpose I/O External Wake Events (GPIO) Pins Programmable Alarm Can be Used to Generate 32 GPIO Pins per Bank (Multiplexed With Internal Interrupts to the PRCM (for Wakeup) or Other Functional Pins) Cortex-A8 (for Event Notification) GPIO Pins Can be Used as Interrupt Inputs Programmable Alarm Can be Used With (up to Two Interrupt Inputs per Bank) External Output (PMIC POWER EN) to Enable Up to Three External DMA Event Inputs that can the Power Management IC to Restore Non-RTC Also be Used as Interrupt Inputs Power Domains Eight 32-Bit General-Purpose Timers Peripherals DMTIMER1 is a 1-ms Timer Used for Up to Two USB 2.0 High-Speed OTG Ports Operating System (OS) Ticks With Integrated PHY DMTIMER4DMTIMER7 are Pinned Out Up to Two Industrial Gigabit Ethernet MACs (10, One Watchdog Timer 100, 1000 Mbps) SGX530 3D Graphics Engine Integrated Switch Tile-Based Architecture Delivering up to 20 Each MAC Supports MII, RMII, RGMII, and Million Polygons per Second MDIO Interfaces Universal Scalable Shader Engine (USSE) is Ethernet MACs and Switch Can Operate a Multithreaded Engine Incorporating Pixel Independent of Other Functions and Vertex Shader Functionality IEEE 1588v2 Precision Time Protocol (PTP) Advanced Shader Feature Set in Excess of Up to Two Controller-Area Network (CAN) Ports Microsoft VS3.0, PS3.0, and OGL2.0 Supports CAN Version 2 Parts A and B Industry Standard API Support of Direct3D Up to Two Multichannel Audio Serial Ports Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, (McASPs) and OpenMax Transmit and Receive Clocks up to 50 MHz Fine-Grained Task Switching, Load Up to Four Serial Data Pins per McASP Port Balancing, and Power Management With Independent TX and RX Clocks Advanced Geometry DMA-Driven Operation Supports Time Division Multiplexing (TDM), for Minimum CPU Interaction Inter-IC Sound (I2S), and Similar Formats Programmable High-Quality Image Anti- Supports Digital Audio Interface Aliasing 2 Device Overview Copyright 20112015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352