Support & Reference Product Order Tools & Technical Community Design Folder Now Documents Software AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717LOCTOBER 2011REVISED MARCH 2020 AM335x Sitara Processors 1 Device Overview 1.1 Features 1 PROFIBUS, PROFINET, EtherNet/IP, and Up to 1-GHz Sitara ARM Cortex -A8 32 Bit More RISC Processor Two Programmable Real-Time Units (PRUs) NEON SIMD Coprocessor 32-Bit Load/Store RISC Processor Capable 32KB of L1 Instruction and 32KB of Data Cache of Running at 200 MHz With Single-Error Detection (Parity) 8KB of Instruction RAM With Single-Error 256KB of L2 Cache With Error Correcting Code Detection (Parity) (ECC) 8KB of Data RAM With Single-Error Detection 176KB of On-Chip Boot ROM (Parity) 64KB of Dedicated RAM Single-Cycle 32-Bit Multiplier With 64-Bit Emulation and Debug - JTAG Accumulator Interrupt Controller (up to 128 Interrupt Enhanced GPIO Module Provides Shift- Requests) In/Out Support and Parallel Latch on External On-Chip Memory (Shared L3 RAM) Signal 64KB of General-Purpose On-Chip Memory 12KB of Shared RAM With Single-Error Controller (OCMC) RAM Detection (Parity) Accessible to All Masters Three 120-Byte Register Banks Accessible by Supports Retention for Fast Wakeup Each PRU External Memory Interfaces (EMIF) Interrupt Controller (INTC) for Handling System mDDR(LPDDR), DDR2, DDR3, DDR3L Input Events Controller: Local Interconnect Bus for Connecting Internal mDDR: 200-MHz Clock (400-MHz Data Rate) and External Masters to the Resources Inside DDR2: 266-MHz Clock (532-MHz Data Rate) the PRU-ICSS DDR3: 400-MHz Clock (800-MHz Data Rate) Peripherals Inside the PRU-ICSS: DDR3L: 400-MHz Clock (800-MHz Data One UART Port With Flow Control Pins, Rate) Supports up to 12 Mbps 16-Bit Data Bus One Enhanced Capture (eCAP) Module 1GB of Total Addressable Space Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT Supports One x16 or Two x8 Memory Device Configurations One MDIO Port General-Purpose Memory Controller (GPMC) Power, Reset, and Clock Management (PRCM) Module Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Controls the Entry and Exit of Stand-By and Selects (NAND, NOR, Muxed-NOR, SRAM) Deep-Sleep Modes Uses BCH Code to Support 4-, 8-, or 16-Bit Responsible for Sleep Sequencing, Power ECC Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Uses Hamming Code to Support 1-Bit ECC Sequencing Error Locator Module (ELM) Clocks Used in Conjunction With the GPMC to Integrated 15- to 35-MHz High-Frequency Locate Addresses of Data Errors from Oscillator Used to Generate a Reference Syndrome Polynomials Generated Using a Clock for Various System and Peripheral BCH Algorithm Clocks Supports 4-, 8-, and 16-Bit per 512-Byte Supports Individual Clock Enable and Disable Block Error Location Based on BCH Control for Subsystems and Peripherals to Algorithms Facilitate Reduced Power Consumption Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Supports Protocols such as EtherCAT , 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717LOCTOBER 2011REVISED MARCH 2020 www.ti.com 2 Peripherals MMC and SD, UART, SPI, I C , Supports Digital Audio Interface Transmission L3, L4, Ethernet, GFX SGX530 , LCD Pixel (SPDIF, IEC60958-1, and AES-3 Formats) Clock) FIFO Buffers for Transmit and Receive (256 Power Bytes) Two Nonswitchable Power Domains (Real- Up to Six UARTs Time Clock RTC , Wake-Up Logic All UARTs Support IrDA and CIR Modes WAKEUP ) All UARTs Support RTS and CTS Flow Three Switchable Power Domains (MPU Control Subsystem MPU , SGX530 GFX , UART1 Supports Full Modem Control Peripherals and Infrastructure PER ) Up to Two Master and Slave McSPI Serial Implements SmartReflex Class 2B for Core Interfaces Voltage Scaling Based On Die Temperature, Up to Two Chip Selects Process Variation, and Performance Up to 48 MHz (Adaptive Voltage Scaling AVS ) Up to Three MMC, SD, SDIO Ports Dynamic Voltage Frequency Scaling (DVFS) 1-, 4- and 8-Bit MMC, SD, SDIO Modes Real-Time Clock (RTC) MMCSD0 has Dedicated Power Rail for 1.8 V Real-Time Date (Day-Month-Year-Day of Week) or 3.3-V Operation and Time (Hours-Minutes-Seconds) Information Up to 48-MHz Data Transfer Rate Internal 32.768-kHz Oscillator, RTC Logic and Supports Card Detect and Write Protect 1.1-V Internal LDO Complies With MMC4.3, SD, SDIO 2.0 Independent Power-on-Reset Specifications (RTC PWRONRSTn) Input 2 Up to Three I C Master and Slave Interfaces Dedicated Input Pin (EXT WAKEUP) for External Wake Events Standard Mode (up to 100 kHz) Fast Mode (up to 400 kHz) Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Up to Four Banks of General-Purpose I/O Cortex-A8 (for Event Notification) (GPIO) Pins Programmable Alarm Can be Used With 32 GPIO Pins per Bank (Multiplexed With External Output (PMIC POWER EN) to Enable Other Functional Pins) the Power Management IC to Restore Non-RTC GPIO Pins Can be Used as Interrupt Inputs Power Domains (up to Two Interrupt Inputs per Bank) Peripherals Up to Three External DMA Event Inputs that can Up to Two USB 2.0 High-Speed DRD (Dual- Also be Used as Interrupt Inputs Role Device) Ports With Integrated PHY Eight 32-Bit General-Purpose Timers Up to Two Industrial Gigabit Ethernet MACs (10, DMTIMER1 is a 1-ms Timer Used for 100, 1000 Mbps) Operating System (OS) Ticks Integrated Switch DMTIMER4DMTIMER7 are Pinned Out Each MAC Supports MII, RMII, RGMII, and One Watchdog Timer MDIO Interfaces SGX530 3D Graphics Engine Ethernet MACs and Switch Can Operate Tile-Based Architecture Delivering up to 20 Independent of Other Functions Million Polygons per Second IEEE 1588v1 Precision Time Protocol (PTP) Universal Scalable Shader Engine (USSE) is Up to Two Controller-Area Network (CAN) Ports a Multithreaded Engine Incorporating Pixel Supports CAN Version 2 Parts A and B and Vertex Shader Functionality Up to Two Multichannel Audio Serial Ports Advanced Shader Feature Set in Excess of (McASPs) Microsoft VS3.0, PS3.0, and OGL2.0 Transmit and Receive Clocks up to 50 MHz Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks Fine-Grained Task Switching, Load Balancing, and Power Management Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction 2 Device Overview Copyright 20112020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351