L138-FI-236-RL Critical Link

Critical Link, LLC MityDSP-L138F System on Module www.CriticalLink.com 21-OCT-2020 FEATURES TI OMAP-L138 Dual Core Application Processor - 456 MHz (Max) C674x VLIW DSP Floating Point DSP 32 KB L1 Program Cache 32 KB L1 Data Cache 256 KB L2 cache 1024 KB boot ROM JTAG Emulation/Debug - 456 MHz (Max) ARM926EJ-S MPU 16 KB L1 Program Cache (actual size) 16 KB L1 Data Cache APPLICATIONS 8 KB Internal RAM Embedded Instrumentation 64 KB boot ROM Industrial Automation JTAG Emulation/Debug Industrial Instrumentation On-Board Xilinx Spartan-6 FPGA Medical Instrumentation - Up To XC6SLX45 Embedded Control Processing Up To 2,088 KBits Block RAM Network Enabled Data Acquisition Up To 6,822 Slices (6 Input LUTs) Test and Measurement - 1050 Mbps data rate Software Defined Radio - JTAG Interface/Debug Bar Code Scanners Power Protection Systems Up To 256 MB mDDR2 CPU RAM Portable Data Terminals Up To 512 MB Parallel NAND FLASH Up to 16 MB SPI based NOR FLASH BENEFITS Integrated Power Management Rapid Development / Deployment Standard SO-DIMM-200 Interface Multiple Connectivity and Interface Options - 96 FPGA User I/O Pins Rich User Interfaces - 10/100 EMAC MII / MDIO High System Integration - 2 UARTS Fixed & Floating Point Operations in Single - 2 McBSPs CPU - 2 USB Ports High Level OS Support - Video Output - Linux - Camera/Video Input - QNX 6.4 - MMC/SD - Windows Embedded CE Ready - SATA - ThreadX Real Time OS - Single 3.3V Power Supply Embedded Digital Signal Processing DESCRIPTION The MityDSP-L138F is a highly configurable, very small form-factor processor card that features a Texas Instruments OMAP-L138 456 MHz (max) Applications Processor (OMAP) tightly integrated with the Xilinx Spartan-6 Field Programmable Gate Array (FPGA), FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The design of the MityDSP-L138F allows end users the capability to develop programs/logic images for both the OMAP and the FGPA. The MityDSP-L138F provides a complete and flexible digital processing infrastructure necessary for the most demanding embedded applications development. 1 Copyright 2013, Critical Link LLC Specifications Subject to Change 60-000037-1B Critical Link, LLC MityDSP-L138F System on Module www.CriticalLink.com 21-OCT-2020 The onboard OMAP-L138 processor provides a dual CPU core topology. The OMAP- L138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich software applications programmer interfaces (APIs) expected by modern system designers. The ARM architecture supports several operating systems, including Linux and Windows Embedded CE. In addition to the ARM core, the OMAP-L138 also includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the DSP to execute real-time compute algorithms (codecs, image/data processing, compression techniques, filtering, etc.). 1.2V Up To 16MB NOR Up To 512MB Up To 256MB 1.8V Flash NAND Flash mDDR Memory Power (SPI interface) 8-bit wide 2.5V 16-bit wide Management For uBoot bootloader For root FFS 3.3V EMIFA (16-bit) System JTAG Clocks JTAG JTAG/Emulator Header Emulator Header MMCSD 1 Texas Instruments Xilinx EMAC RMII OMAP-L138 Spartan-6 UHPI 456-MHz ARM926EJ-S RISC MPU FPGA 456-MHz C674x VLIW DSP uPP Up To XC6SLX45 LCD CSG324 pkg. (Many pins are multiplexed between peripherals) VPIF I/O Boot Config FPGA I/O Banks can be 1.8V, 2.5V, or 3.3V SO-DIMM-200 (DDR2 Connector) Figure 1 MityDSP-L138F Block Diagram Figure 1 provides a top level block diagram of the MityDSP-L138F processor card. As shown in the figure, the primary interface to the MityDSP-L138F is through a standard SO-DIMM-200 card edge interface. The interface provides power, synchronous serial connectivity, and up to 96 pins of configurable FPGA I/O for application defined interfacing. Details of the SO-DIMM-200 connector interface are included in the SO- DIMM-200 Interface Description, as shown below. 2 Copyright 2013, Critical Link LLC Specifications Subject to Change 60-000037-1B EMAC MII/MDIO MMCSD 0 UART 0,1,2 McBSP 0,1 SPI 0,1 I2C 0,1 McASP eCAP eHRPWM Timers SATA USB 0,1 Resets & RTC Boot Config I/O Bank Power Programmable I/O I/O Bank Power Programmable I/O 3.3 V GND