DTM64605B 2GB - 204-pin 1Rx8 Unbuffered Non-ECC DDR3 SO-DIMM Identification DTM64605B 256Mx64 2GB 1Rx8 PC3-10600S-9-11-B2 Performance range Clock / Module Speed / CL-t -t RCD RP 667 MHz / DDR3-1333 / 9-9-9 533 MHz / DDR3-1066 / 8-8-8 533 MHz / DDR3-1066 / 7-7-7 400 MHz / DDR3-800 / 6-6-6 333 MHz / DDR3-667 / 5-5-5 Features Description 204-pin SO-DIMM. Dual-sided assembly 67.60 mm 2.661 wide DTM64605B is a non-ECC Unbuffered by 30.0 mm 1.181 high DDR3-1333, 256Mx64 memory module. The Operating Voltage: 1.5 V 0.075 V assembly is a one rank SO-DIMM comprised of eight Samsung 256Mx8 DDR3 SDRAMs. I/O Type: SSTL 15 One 2K-bit EEPROM is used for Serial Data Transfer Rate: 10.6 Gigabytes/sec Presence Detect. Both output driver strength and input Data Bursts: 8 and burst chop 4 mode termination impedance are programmable to ZQ Calibration for Output Driver and On-Die Termination (ODT) maintain signal integrity on the I/O signals. Programmable ODT / Dynamic ODT during Writes The assembly is a Small Outline Dual In-line Memory Module intended for mounting into Programmable CAS Latency: 5, 6, 7, 8 and 9 204-pin edge connector sockets. Bi-directional Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 15/10/3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 V 53 DQ19 105 V 157 DQ42 2 V 54 V 106 V 158 DQ46 DQ 63:0 Data Bits REFDQ DD SS SS DD 3 V 55 V 107 A10/AP 159 DQ43 4 DQ4 56 DQ28 108 BA1 160 DQ47 DQS 7:0 , /DQS 7:0 Differential Data Strobes SS SS 5 DQ0 57 DQ24 109 BA0 161 V 6 DQ5 58 DQ29 110 /RAS 162 V DM 7:0 Data Mask SS SS 7 DQ1 59 DQ25 111 V 163 DQ48 8 V 60 V 112 V 164 DQ52 CK 1:0 , /CK 1:0 Differential Clock Inputs DD SS SS DD 9 V 61 V 113 /WE 165 DQ49 10 /DQS0 62 /DQS3 114 /S0 166 DQ53 CKE0 Clock Enables SS SS 11 DM0 63 DM3 115 /CAS 167 V 12 DQS0 64 DQS3 116 ODT0 168 V /CAS Column Address Strobe SS SS 13 V 65 V 117 V 169 /DQS6 14 V 66 V 118 V 170 DM6 /RAS Row Address Strobe SS SS DD SS SS DD 15 DQ2 67 DQ26 119 A13 171 DQS6 16 DQ6 68 DQ30 120 NC 172 V /S0 Chip Selects SS 17 DQ3 69 DQ27 121 NC 173 V 18 DQ7 70 DQ31 122 NC 174 DQ54 /WE Write Enable SS 19 V 71 V 123 V 175 DQ50 20 V 72 V 124 V 176 DQ55 A 15:0 Address Inputs SS SS DD SS SS DD 21 DQ8 73 CKE0 125 NC/TEST 177 DQ51 22 DQ12 74 NC 126 V 178 V BA 2:0 Bank Addresses REFCA SS 23 DQ9 75 V 127 V 179 V 24 DQ13 76 V 128 V 180 DQ60 ODT0 On Die Termination Inputs DD SS SS DD SS 25 V 77 NC 129 DQ32 181 DQ56 26 V 78 A15* 130 DQ36 182 DQ61 SA 1:0 SPD Address SS SS 27 /DQS1 79 BA2 131 DQ33 183 DQ57 28 DM1 80 A14 132 DQ37 184 V SCL SPD Clock Input SS 29 DQS1 81 V 133 V 185 V 30 /RESET 82 V 134 V 186 /DQS7 SDA SPD Data Input/Output DD SS SS DD SS 31 V 83 A12/BC 135 /DQS4 187 DM7 32 V 84 A11 136 DM4 188 DQS7 TEST Logic Analyzer specific SS SS 33 DQ10 85 A9 137 DQS4 189 V 34 DQ14 86 A7 138 V 190 V EVENT Output of the Thermal Sensor SS SS SS 35 DQ11 87 V 139 V 191 DQ58 36 DQ15 88 V 140 DQ38 192 DQ62 V Ground DD SS DD SS 37 V 89 A8 141 DQ34 193 DQ59 38 V 90 A6 142 DQ39 194 DQ63 V Power SS SS DD 39 DQ16 91 A5 143 DQ35 195 V 40 DQ20 92 A4 144 V 196 V V SPD EEPROM Power SS SS SS DDSPD 41 DQ17 93 V 145 V 197 SA0 42 DQ21 94 V 146 DQ44 198 EVENT* V Reference Voltage for DQ DD SS DD REFDQ 43 V 95 A3 147 DQ40 199 V 44 V 96 A2 148 DQ45 200 SDA V Reference Voltage for CA SS DDSPD SS REFCA 45 /DQS2 97 A1 149 DQ41 201 SA1 46 DM2 98 A0 150 V 202 SCL V Termination Voltage SS TT 47 DQS2 99 V 151 V 203 V 48 V 100 V 152 /DQS5 204 V NC No Connection DD SS TT SS DD TT 49 V 101 CK0 153 DM5 50 DQ22 102 CK1* 154 DQS5 SS 51 DQ18 103 /CK0 155 V 52 DQ23 104 /CK1* 156 V SS SS * = Not Used Document 06845, Revision A, 12-Aug-11, Dataram Corporation 2011 Page 1 DTM64605B 2GB - 204-pin 1Rx8 Unbuffered Non-ECC DDR3 SO-DIMM Front view 67.600 2.661 30.000 1.181 20.000 4.000 .787 .157 2.150 3.000 2.540 Min .130 .100 Min .118 21.150 39.000 .833 1.535 63.000 2.480 Side view Back view 3.80 Max .150 Max 4.000 Min .157 Min 1.000 .100 .040 .004 Notes Tolerances on all dimensions except where otherwise indicated are .13 (.005). All dimensions are expressed: millimeters inches Document 06845, Revision A, 12-Aug-11, Dataram Corporation 2011 Page 2