74LVC574A OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS Description Pin Assignments The 74LVC574A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high- impedance state. Applications These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. General Purpose Logic Bus Driving The device is designed for operation with a power supply range of Power Down Signal Isolation 1.65V to 3.6V. The device is fully specified for partial power down Wide Array of Products Such as: applications using I . OFF PCs, Notebooks, Netbooks, Ultrabooks Networking Computer Peripherals, Hard Drives, CD/DVD Features ROM Supply Voltage Range from 1.65V to 3.6V TV, DVD, DVR, set top box Sinks or Sources 24mA at V = 3V CC CMOS Low Power Consumption I Supports Partial-Power Down Operation OFF Inputs or Outputs Accept Up to 5.5V Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications Schmitt Trigger Action at All Inputs Typical V (Quiet Output Ground Bounce) less than 0.8V with OLP V = 3.3V and T = +25C CC A Typical V (Quiet Output Dynamic VOH) greater than 2.0V OHV with V = 3.3V and T = +25C CC A ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115) Exceeds 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101) Latch-Up Exceeds 250mA per JESD 78, Class I All devices are: Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See 74LVC574A Ordering Information 74 LVC 574A xxx -13 Logic Device Function Package Packing 74 : Logic Prefix 574 : Octal D-Type T20 : TSSOP-20 -13 : 13 Tape & Reel Flip-Flop with 3 Q20 : QFN-20 State Outputs Package 13 Tape and Reel Package Package Part Number Size Code (Note 4 & 5) Quantity Part Number Suffix 6.4mm X 6.5mm X 1.2mm 74LVC574AT20-13 T20 TSSOP-20 2500/Tape & Reel -13 0.65 mm lead pitch 2.5mm X 4.5mm X 0.95mm 74LVC574AQ20-13 Q20 V-QFN4525-20 2500/Tape & Reel -13 0.50 mm lead pitch Notes: 4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at