PI4MSD5V9547LEX Diodes Incorporated

PI4MSD5V9547 8 Channel I2C bus multiplexer with Reset Features Description 1-of-8 bidirectional translating multiplexer The PI4MSD5V9547 is an octal bidirectional I2C-bus interface logic translating multiplexer controlled by the I2C-bus. The Operating power supply voltage from 1.65V to SCL/SDA upstream pair fans out to eight downstream 5.5V pairs, or channels. Allows voltage level translation between 1.2V, Only one SCx/SDx channel can be selected at a time, 1.8V,2.5 V, 3.3 V and 5 V buses determined by the contents of the programmable control Low standby current register. The device powers up with Channel 0 Low Ron switches connected, allowing immediate communication between Active LOW reset input the master and downstream devices on that channel. Channel selection via I2C bus An active LOW reset input allows the Power-up with one channel on PI4MSD5V9547 to recover from a situation where one Capacitance isolation when channel disabled of the downstream I2C-buses is stuck in a LOW state. No glitch on power-up Pulling the RESET pin LOW resets the I2C-bus state Supports hot insertion machine and causes all the channels to be deselected as 5 V tolerant inputs does the internal Power-On Reset (POR) function. 0 Hz to 400 kHz clock frequency The pass gates of the switches are constructed such ESD protection exceeds 8000 V HBM per JESD22- that the VCC pin can be used to limit the maximum high A114, and 1000 V CDM per JESD22-C101 voltage which is passed by the PI4MSD5V9547. This Latch-up testing is done to JEDEC Standard allows the use of different bus voltages on each pair, so JESD78 which exceeds 100 mA that1.2V, 1.8 V or 2.5 V or 3.3 V parts can communicate Packages offered: TSSOP-24L,TQFN-24ZD with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. Pin Configuration TSSOP TQFN 2016-06-0003 PT0544-3 09/02/16 1 PI4MSD5V9547 8 Channel I2C bus multiplexer with Reset Pin Description Pin No. Pin No. (TSSOP, Pin Name Type Description (TQFN) SOIC) 1 22 A0 I address input 0 2 23 A1 I address input 1 3 24 I active LOW reset input RESET 4 1 SD0 I/O serial data 0 T 5 2 SC0 I/O serial clock 0 6 3 SD1 I/O serial data 1 7 4 SC1 I/O serial clock 1 8 5 SD2 I/O serial data 2 9 6 SC2 I/O serial clock 2 10 7 SD3 I/O serial data 3 11 8 SC3 I/O serial clock 3 12 9 GND Ground supply ground 13 10 SD4 I/O serial data 4 14 11 SC4 I/O serial clock 4 15 12 SD5 I/O serial data 5 16 13 SC5 I/O serial clock 5 17 14 SD6 I/O serial data 6 18 15 SC6 I/O serial clock 6 19 16 SD7 I/O serial data 7 20 17 SC7 I/O serial clock 7 21 18 A2 I address input 2 22 19 SCL I/O serial clock line 23 20 SDA I/O serial data line 24 21 VCC Power supply voltage 2016-06-0003 PT0544-3 09/02/16 2