PI6C41204 PI6C41204A 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 LVCMOS to LVPECL Driver Description Features PI6C41204 & PI6C41204A are high-performance LVCMOS or Up to Four LVPECL outputs LVTTL to LVPECL clock buffers. The PI6C41204 is a 4 output Selectable CLK0 or CLK1 inputs version with 2 selectable inputs, pin compatible with ICS8535-01. LVCMOS or LVTTL input level PI6C41204A is the enhanced version with extra power and 30ps max output skew ground pins to minimize noise and jitter. 150ps max part-to-part skew 1.9ns max propagation delay 266 MHz output frequency Packaging (Pb-free & Green available): - 20-pin TSSOP Block Diagram PI6C41204/A Pin Configuration PI6C41204/A D Q0 Vee 1 20 CLK EN Q CLK EN nQ0 2 19 LE CK SEL 3 18 Vcc 0 CLK0 Q0 CLK0 4 17 Q1 nQ0 CLK1 1 20-Pin nc/Vee 5 16 nQ1 Q1 CLK1 6 15 Q2 nQ1 CLK SEL nc/Vee 7 14 nQ2 Q2 nc/Vee 8 13 Vcc nQ2 nc/Vcc 9 12 Q3 Q3 Vcc 10 11 nQ3 nQ3 PS8626E 11/18/08 08-0304 1PI6C41204/PI6C41204A LVCMOS to LVPECL Driver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Table 1a. Pin Description for PI6C41204 NeumberNeamTnyp Descriptio 1eVreP.owe Ground Synchronizing clock enable. When HIGH, clock outputs follow 2NCtLK EIpnpu Pullu clock input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL input level. Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS 3LCtLK SEInnpu Pulldow or LVTTL input level. 40CtLKInnpuP.ulldow LVCMOS or LVTTL clock input 61CtLKInnpuP.ulldow LVCMOS or LVTTL input level 5C, 7, 8, 9NdUtnuse No Connec 1c0, 13, 18VrcPyowe 3.3V suppl 131, 12ntQ3, QO.utpu LVPECL output pair 124, 15ntQ2, QO.utpu LVPECL output pair 116, 17ntQ1, QO.utpu LVPECL output pair 109, 20ntQ0, QO.utpu LVPECL output pair Table 1b. Pin Description for PI6C41204A NeumberNeamTnyp Descriptio 1e, 5, 7, 8VreP.owe Ground Synchronizing clock enable. When HIGH, clock outputs follow 2NCtLK EIpnpu Pullu clock input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL input level. Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS 3LCtLK SEInnpu Pulldow or LVTTL input level 40CtLKInnpuP.ulldow LVCMOS or LVTTL clock input 61CtLKInnpuP.ulldow LVCMOS or LVTTL input level 9, 10, 13, VrccPyowe 3.3V suppl 18 131, 12ntQ3, QO.utpu LVPECL output pair 124, 15ntQ2, QO.utpu LVPECL output pair 116, 17ntQ1, QO.utpu LVPECL output pair 109, 20ntQ0, QO.utpu LVPECL output pair PS8626E 11/18/08 08-0304 2