V PI90LV14/PI90LVT14 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5 Clock Distribution Features Description Meets and Exceeds the Requirements of ANSI The PI90LV14 implements low voltage differential signaling (LVDS) TIA/EIA-644-1995 to achieve clocking rates as high as 320MHz with low skew. Designed for clocking rates up to 320MHz Operates from a single 3.3V Supply The PI90LV14 is a low-skew 1:5 clock distribution chip which Low Voltage Differential Signaling (LVDS) with Output incorporates multiplexed clock inputs to allow for distribution of a Voltages of 350mV into a 100-ohm load lower-speed, single-ended clock or a high-speed system clock. Choice between LVDS or TTL clock input When LOWthe SEL pin will select the differential clock input. Synchronous Enable/Disable The common enable (EN) is synchronous so that the outputs will Clock outputs default LOW when inputs open only be enabled/disabled when they are already in the LOW state. Multiplexed clock input This avoids any chance of generating a runt clock pulse when the Internal 300kohms pullup resistor on input pins device is enabled/disabled as can happen with an asynchronous CLK & CLK have 110-ohm internal termination (PI90LVT14) control. Because the internal flip-flop is clocked on the falling edge 50ps Output-to-Output Skew of the input clock, all associated specification limits are referenced 475ps typical propagation delay to the negative edge of the clock input. 22ps Period Jitter The intended application of these devices and signaling technique Bus Pins are high impedance when disabled or with V less CC than 1.5V is for high-speed clock distribution between boards. TTL inputs are 5V Tolerant Power Dissipation at 400Mbits/s of 150mW Function compatible to Motorola (PECL) MC100EL14 and Micrel/Synergy (PECL) PI90LV14 Block Diagram SY100EL14V >9kV ESD Protection 1 CLK1 20-pin TSSOP (L) (Pb-free available) OUT+ 20 VCC 2 CLK1 OUT Pin Descriptions 19 EN Pnin Functio 3 CLK2 OUT+ D CsLK, CLK Differential Clock Input V 18 CC 4 Q CLK2 OUT 17 GND StCLK LVTTL Clock Inpu EeN Synchronous Enabl 5 16 1 CLK3 SCLK OUT+ StEL Clock Select Inpu 15 6 CLK CLK3 OUT CLK1-5 Differential Clock Outputs OUT 1107 PI90LVT14 Only Function Table 14 0 7 CLK CLK4 OUT+ CKLKSLCL S*EE+N CLKOUT 8 13 GND CLK4 OUT LX L L L 12 SEL HX L L H 9 CLK5 OUT+ XL H L L 10 CLK5 OUT XH H L H 11 GND XH Z* * On next negative transition of CLK, or SCLK 08-0295 PS8538D 10/27/09 1PI90LV14/PI90LVT14 1:5 Clock Distribution 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted). (1) SrymbolPsaramete T.est Condition M.in Typ Msax. Unit V Differential output voltage magnitude 2047 344 45 OD R = 100 L mV Change in differential output voltage See Figures 1 and 2 V 050 5 OD magnitude between logic states Steady-state common-mode output V 10.12517.4 1V. OC(SS) voltage Change in steady-state common-mode V See Figure 3 050 5 OC(SS) output voltage between logic states mV Peak-to-peak common-mode V 600 10 OC(PP) output voltage Enabled, R = 100 V = Vo1r GND 253 L IN CC I Supply Current mA CC Disabled, V = Vo5r GND 05. 20. 4. IN CC IHVigh-level input current=02V 30. 2 IH IH A ILVow-level input current=00.8V 5. 20 IL IL V or V = 0V 7.4 ODOUT+ ODOUT I Short-circuit output current mA OS V = 0V 4.7 OD IHVigh-impedance output current = 0V or V 1 OZ O CC A IPVower-off output current = 1.1V, V=12.4V O(OFF) CC O CIVnput capacitance, = 0.4 sin (4E6t9) +0.5V IN I pF COVutput capacitance = 0.4 sin (4E6t0) +0.5V, Disabled 1 O I RT4ermination ResistorP0I90LVT1 90121 13 TERM 08-0295 PS8538D 10/27/09 2