PT7C4511WEX Diodes Incorporated

PT7C4511 PLL Clock Multiplier Features Description Block Diagram OE S0 PLL Clock Synthesis Output and CLK Buffer S1 Control Circuit X1/ICLK Crystal X2 Oscillator V GND CC Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See PT7C4511 Pin Configuration 1 8 X1/ICLK X2 2 Vcc OE 7 3 6 GND S0 4 S1 CLK 5 SOIC-8 package Pin Description Pin Name Pin Type Description X1/ICLK 1 X1 Crystal connection or clock input. Vcc 2 P Connect to +3.3V or +5V. GND 3 P Connect to ground. S1 4 T1 Multiplier select pin, connect to GND or Vcc or floating (no connection). CLK 5 O Clock output per Table below. S0 6 T1 Multiplier select pin 0, connect to GND or Vcc or floating (no connection). OE 7 I Output enable, tri-state CLK output when low. Internal pull-up. X2 8 XO Crystal connection. Leave unconnected for clock input. Clock Output Table S1 S0 CLK 0 0 4 0 M (16/3) 0 1 5 M 0 2.5 M M 2 M 1 (10/3) 1 0 6 1 M 3 1 1 8 1) Note: CLK output frequency=ICLK 4. 2) Note: M=Leave unconnected (self-biases to Vcc/2). PT7C4511 www.diodes.com July 2020 Document Number DS42386 Rev 1-2 Diodes Incorporated 2