Short Form Data Sheet April 2012 DS31407 3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description Features Three Input Clocks The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and frequency Differential or CMOS/TTL Format synthesis applications. On each of its three input clocks Any Frequency from 2kHz to 750MHz and four output clocks, the device can accept or Fractional Scaling for 64B/66B and FEC generate nearly any frequency between 2kHz and Scaling (e.g., 64/66, 237/255, 238/255) or Any 750MHz. Other Downscaling Requirement Continuous Input Clock Quality Monitoring The input clocks are divided down, fractionally scaled as Automatic or Manual Clock Selection needed, and continuously monitored for activity and Three 2/4/8kHz Frame Sync Inputs frequency accuracy. The best input clock is selected, High-Performance DPLL manually or automatically, as the reference clock for the Hitless Reference Switching on Loss of Input rest of the device. A flexible, high-performance digital Automatic or Manual Phase Build-Out PLL locks to the selected reference and provides Holdover on Loss of All Inputs programmable bandwidth, very high resolution holdover Programmable Bandwidth, 0.5mHz to 400Hz capability, and truly hitless switching between input Two Digital Frequency Synthesizers clocks. The digital PLL is followed by a clock synthesis Produce Any 2kHz Multiple Up to 77.76MHz subsystem that has two fully programmable digital Per-DFS Clock Phase Adjust frequency synthesis blocks, a high-speed low-jitter APLL, and four output clocks, each with its own 32-bit High-Performance Output APLL divider and phase adjustment. The APLL provides Output Frequencies to 750MHz fractional scaling and output jitter less than 1ps RMS. High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) For telecom systems, the DS31407 has all required or Any Other Scaling Requirement features and functions to serve as a central timing Less than 1ps RMS Output Jitter function or as a line card timing IC. With a suitable Four Output Clocks in Two Groups oscillator the DS31407 meets the requirements of Nearly Any Frequency from < 1Hz to 750MHz Stratum 2, 3E, 3, 4E, and 4, G.812 Types IIV, G.813, Each Group Slaves to a DFS Clock, an APLL and G.8262. Clock, or Any Input Clock (Divided and Scaled) Each Has a Differential Output (1 CML, 1 LVDS/ LVPECL) and Separate CMOS/TTL Output Applications 32-Bit Frequency Divider Per Output Frequency Conversion Applications in a Wide Variety of Two Sync Pulse Outputs: 8kHz and 2kHz Equipment Types General Features Telecom Line Cards or Timing Cards with Any Mix of Suitable Line Card IC or Timing Card IC for SONET/SDH, Synchronous Ethernet and/or OTN Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU Ports in WAN Equipment Including MSPPs, Ethernet Accepts and Produces Nearly Any Frequency Up Switches, Routers, DSLAMs, and Base Stations to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, Ordering Information 156.25M, and Nx19.44M Up to 622.08M PART TEMP RANGE PIN-PACKAGE Internal Compensation for Local Oscillator Frequency Error DS31407GN+ -40 C to +85 C 256 CSBGA SPI Processor Interface +Denotes a lead(Pb)-free/RoHS-compliant package. 1.8V Operation with 3.3V I/O (5V Tolerant) SPI is a trademark of Motorola, Inc. 1 Short Form Data Sheet DS31407 Application Example clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional scaling, jitter attenuation Output clocks can be nearly any frequency from <1Hz to 725MHz. Each output clock can be sourced from a DFS block, an APLL or Each input can be any frequency from an input clock (divided and scaled). from 2kHz to 725MHz Each output clock has its own 32-bit divider. OC1 IC1 OC1POS/NEG Output Cocks system timing outputs from APLL: <1ps rms jitter, OC4 from master and slave DS31407 IC2 outputs from DFS: ~40ps rms jitter timing cards OC4POS/NEG Block Diagram DS31407 SYNC1 FSYNC SYNC2 MFSYNC MFSYNC SYNC3 PLL Bypass DFS Muxes Divider Muxes Dif Mux Input Clock DFS 1 Divider 1 OC1 Block DPLL IC1 POS/NEG OC1POS/NEG Filtering, Holdover, APLL1 lowest jitter path 3 Hitless Switching, PBO, IC2 POS/NEG Frequency Scaler, Frequency Conversion, Activity Monitor, Manual Phase Adjust IC3 POS/NEG Freq. Monitor, OC4 Optional Inversion DFS 4 Clock Divider 4 status (per input clock) OC4POS/NEG Selector JTRST Master Clock Microprocessor Port JTMS JTCLK JTAG (SPI Serial) APLL JTDI and HW Control and Status Pins JTDO MCLKOSC Local Oscillator TCXO or OCXO 2 RST TEST SRCSW INTREQ SRFAIL LOCK GPIO 4:1 CS SCLK SDO SDI CPHA CPOL OSCFREQ 2:0