REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Delete programming waveforms, 4.5.1, 4.5.2, and table III. Changes to 4.5 and 90-06-25 M. Poelking 6.6. Editorial changes throughout. Redrawn. D Change C and C in table I, IAW NOR 5962-R003-9l. 91-09-20 M. A. Frye IN OUT E Add device type 05 editorial changes throughout. Redrawn. 93-02-02 M. A. Frye F Add device type 06 editorial changes throughout. Redrawn. 93-05-04 M. A. Frye G Changes in accordance with NOR 5962-R187-93 93-06-17 M. A. Frye H Changes in accordance with NOR 5962-R207-93 93-07-29 M. A. Frye J Update drawing to current requirements. Editorial changes throughout. - gap 02-01-04 Raymond Monnin K Boilerplate update, part of 5 year review. ksr 08-04-25 Robert M. Heber L 10-03-29 Charles F. Saffle Corrected I and I parameters in Table I. ksr IL IH THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV L SHEET 15 REV STATUS REV L L L L L L L L L L L L L L OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY COLUMBUS, OHIO 43218-3990 STANDARD 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87539 01 X A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function t PD 01 C22V10 22-input 10-output AND-OR-logic array 25 ns 02 C22V10 22-input 10-output AND-OR-logic array 30 ns 03 C22V10 22-input 10-output AND-OR-logic array 40 ns 04 C22V10 22-input 10-output AND-OR-logic array 20 ns 05 C22V10 22-input 10-output AND-OR-logic array 15 ns 06 C22V10 22-input 10-output AND-OR-logic array 10 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24, CDFP3-F24 24 Flat package 1/ L GDIP3-T24, CDIP4-T24 24 Dual-in-line package 1/ 3 CQCC1-N28 28 Square chip carrier package 1/ X GQCC1-J28 28 lead chip carrier package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range ................................................................. -0.5 V dc to +7.0 V dc Input voltage range .................................................................... -2.0 V dc to +7.0 V dc 3/ Output voltage applied range .................................................... -0.5 V dc to +7.0 V dc 3/ Output sink current .................................................................... 16 mA Thermal resistance, junction-to-case ( ) ................................ See MIL-STD-1835 JC Maximum power dissipation (P ) 4/ ........................................... 1.2 W D Maximum junction temperature ................................................. +175C Lead temperature (soldering, 10 seconds maximum) ................ +260C 1.4 Recommended operating conditions. Supply voltage range (V ) ....................................................... 4.5 V dc to 5.5 V dc CC High level input voltage (V ) ..................................................... 2.0 V dc minimum IH Low level input voltage (V ) ...................................................... 0.8 V dc maximum IL 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to V . SS 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is V +0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. CC 4/ Must withstand the added P due to short circuit test e.g., I . D OS SIZE STANDARD 5962-87539 A MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 L 2 DSCC FORM 2234 APR 97