MR0D08B Dual Supply 128K x 8 MRAM FEATURES +3.3 Volt power supply I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces Fast 45 ns read/write cycle SRAM compatible timing Unlimited read & write endurance Data always non-volatile for >20-years at temperature RoHS-compliant small footprint BGA package BENEFITS One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems RoHS for simpler, more efficient designs Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR0D08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM) de- vice organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The MR0D08B offers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to pre- vent writes with voltage out of specification. The MR0D08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0D08B is available in small footprint 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. The MR0D08B provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature (0 to +70 C). CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 8 4. ORDERING INFORMATION....................................................................... 13 5. MECHANICAL DRAWING.......................................................................... 14 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.......................................................................................... 15 CCopopyryrighight Et Evverspin erspin TTechnologechnologies 2018ies 2015 11 MR0D08B Rev. 3.3, 3/2018MR0D08B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT G ENABLE OUTPUT ENABLE BUFFER 7 A 16:0 ADDRESS 10 ROW BUFFER COLUMN 17 DECODER DECODER CHIP E 8 OUTPUT 8 8 ENABLE SENSE BUFFER BUFFER AMPS 128Kx 8 BIT MEMORY WRITE W ARRAY ENABLE FINAL BUFFER 8 8 WRITE 8 WRITE DQ 7:0 DRIVER DRIVERS WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O V Power Supply DD V I/O Power Supply DDQ V Ground SS DC Do Not Connect NC No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion Copyright Everspin Technologies 2018 2 MR0D08B Rev. 3.3, 3/2018