MR20H40 / MR25H40 t MR20H40 - 50MHz/20ns SCK 4Mb SPI Interface MRAM t MR25H40 - 40MHz/25ns SCK 4Mb SPI Interface MRAM For more information on product options, see Table 16 Ordering Part Numbers on page 25. FEATURES No write delays Unlimited write endurance Data retention greater than 20 years Automatic data protection on power loss 8-DFN Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40. 3.0 to 3.6 Volt power supply range Low-current sleep mode Commercial (0 to 70C), Industrial (-40 to 85C), Extended (-40 to 105C), and 8-DFN Small Flag AEC-Q100 Grade 1 (-40 to 125C) temperature range options. Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant packages. Direct replacement for serial EEPROM, Flash, and FeRAM RoHS MSL Level 3 DESCRIPTION MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE- PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur randomly in memory with no delay between writes. The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The MR20H40 (50MHz) is offered with Industrial (-40 to 85 C) range. The MR25H40 (40MHz) is offered with Commercial (0 to 70C), Industrial (-40 to 85 C), Extended (-40 to 105C), and AEC-Q100 Grade 1 (-40C to 125 C) operating temperature range options. Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM, EEPROM, Flash, and FeRAM products. Copyright Everspin Technologies 2020 1 MR20H40 / MR25H40 Revision 12.6, 8/2020MR20H40 / MR25H40 TABLE OF CONTENTS OVERVIEW ............................................................................................................................................5 Figure 1 Block Diagram ........................................................................................................................................... 5 System Configuration .....................................................................................................................5 Figure 2 System Configuration ............................................................................................................................. 5 Pin Functions ...................................................................................................................................6 Figure 3 DFN Package Pin Diagram (Top View) .............................................................................................. 6 Table 1 Pin Functions ............................................................................................................................................... 6 SPI COMMUNICATIONS PROTOCOL ...................................................................................................7 Command Codes ..............................................................................................................................7 Table 2 Command Codes ....................................................................................................................................... 7 Status Register, Memory Protection and Block Write Protection ................................................8 Table 3 Status Register Bit Assignments ........................................................................................................... 8 Memory Protection Modes .............................................................................................................8 Table 4 Memory Protection Modes .................................................................................................................... 8 Block Protection Modes ..................................................................................................................9 Table 5 Block Memory Write Protection ............................................................................................................ 9 Read Status Register (RDSR) ........................................................................................................ 10 Figure 4 Read Status Register (RDSR) Timing ................................................................................................10 Write Enable (WREN) .................................................................................................................... 10 Figure 5 Write Enable (WREN) Timing ..............................................................................................................10 Write Disable (WRDI) .................................................................................................................... 11 Figure 6 Write Disable (WRDI) Timing ..............................................................................................................11 Write Status Register (WRSR) ...................................................................................................... 11 Figure 7 Write Status Register (WRSR) Timing ..............................................................................................11 Read Data Bytes (READ) ............................................................................................................... 12 Figure 8 Read Data Bytes (READ) Timing ........................................................................................................12 Copyright Everspin Technologies 2020 2 MR20H40 / MR25H40 Revision 12.6 8/2020