MR2A08A 512K x 8 MRAM Memory FEATURES Fast 35ns Read/Write Cycle SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign Unlimited Read & Write Endurance Data Always Non-volatile for >20 years at Temperature One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in System for Simpler, More Efficient Design Replace battery-backed SRAM solutions with MRAM to eliminate battery assembly, improving reliability 3.3 Volt Power Supply Automatic Data Protection on Power Loss Commercial, Industrial, Automotive Temperatures RoHS-Compliant SRAM TSOP2 Package RoHS-Compliant SRAM BGA Package AEC-Q100 Grade 1 Qualified RoHS INTRODUCTION The MR2A08A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 524,288 words of 8 bits. The MR2A08A offers SRAM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR2A08A is the ideal memory solution for applications that must permanently store and retrieve criti- cal data and programs quickly. The MR2A08A is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type 2 package or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR2A08A provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature range (0 to +70 C), industrial temperature range (-40 to +85 C), and AEC-Q100 Grade 1 temperature range (-40 to +125 C) options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 11 5. MECHANICAL DRAWING.......................................................................... 12 6. REVISION HISTORY...................................................................................... 14 How to Reach Us.......................................................................................... 14 Copyright 2018 Everspin Technologies, Inc. 1 MR2A08A Rev. 6.3, 3/2018MR2A08A 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT G ENABLE OUTPUT ENABLE BUFFER 9 A 18:0 ADDRESS 10 ROW BUFFER COLUMN 19 DECODER DECODER CHIP E 8 OUTPUT 8 8 ENABLE SENSE BUFFER BUFFER AMPS 512k x 8 BIT MEMORY WRITE W ARRAY ENABLE FINAL BUFFER 8 8 WRITE 8 WRITE DQ 7:0 DRIVER DRIVERS WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O V Power Supply DD V Ground SS DC Do Not Connect NC No Connection - Pin 2, 43 (TSOPII) Ball H6, G2 (BGA) Reserved For Future Expansion Copyright 2018 Everspin Technologies, Inc. 2 MR2A08A Rev. 6.3, 3/2018