MR3A16A 512K x 16 MRAM FEATURES +3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Unlimited read & write endurance Data always non-volatile for >20 years at temperature RoHS-compliant small footprint BGA and TSOP2 package All products meet MSL-3 moisture sensitivity level BENEFITS One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR3A16A is a 8,388,608-bit magnetoresistive random access memory RoHS (MRAM) device organized as 524,288 words of 16 bits. The MR3A16A offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automatically protect- ed on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR3A16A is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR3A16A is available in a small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR3A16A provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C), and industrial temperature (-40 to +85 C) operating temperature options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 3 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 12 5. MECHANICAL DRAWING.......................................................................... 13 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.............................................................................................. 16 Copyright 2020 Everspin Technologies, Inc. 1 MR3A16A Rev. 1.1 03/2020MR3A16A 1. DEVICE PIN ASSIGNMENT Figure 1.0 Block Diagram OUTPUT G UPPER BYTE OUTPUT ENABLE ENABLE BUFFER LOWER BYTE OUTPUT ENABLE 9 UPPER A 18:0 ADDRESS 8 BYTE 10 ROW BUFFER COLUMN 19 OUTPUT DECODER 8 DECODER BUFFER SENSE CHIP E LOWER 16 AMPS 8 ENABLE BYTE 8 OUTPUT BUFFER 512 x 16 BUFFER BIT UPPER MEMORY 8 BYTE WRITE DQU 15:8 W 8 ARRAY WRITE ENABLE DRIVER FINAL BUFFER 16 WRITE 8 LOWER DRIVERS 8 BYTE DQL 7:0 WRITE DRIVER UB UB UPPER BYTE WRITE ENABLE BYTE ENABLE LB LB BUFFER LOWER BYTE WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O V Power Supply DD V Ground SS DC Do Not Connect NC No Connection Copyright 2020 Everspin Technologies, Inc. 2 MR3A16A Rev. 1.1 03/2020