FTLX1671D3BTL Finisar

PPRELIMMINARYY Producct Specifification RoHS--6 Complliant 10GGb/s Induustrial Teemperatuure 40kmm Datacomm SFP+ Transceiiver FTLX1671D3BBTL PROODUCT FEAATURES Hot-plugggable SFP+ ffootprint Supports 9.95 to 10.3Gb/s bit ratees Power disssipation < 11.5W Typical <<1W RoHS-6 ccompliant (leead-free) Industriall temperaturee range -40C to 885C Single 3.33V power suupply Maximumm link lengthh of 40km Preliminnary photo showwn. TM 1550nm ccooled CMLL technologgy APPLLICATIONSS Receiver limiting elecctrical interface 100GBASE-ERR/EW 10G EEthernet Duplex LC connectorr Built-in ddigital diagnoostic functions Finisars FTLX11671D3BTLL 10Gb/s EEnhanced Smmall Form Factor Plugggable SFPP+ transcceivers are designed foor use in 10--Gigabit Ethhernet links up to 40kmm over singlle 1 2 modee fiber. TThey are coompliant wiith SFF-84331 , SFF-84432 and IEEEE 802.3aae 3 10GBBASE-ER/EW . The FTTLX1671D3BBTL incorpoorates advannced CML technologyy, and iis a limitinng module, i.e., it empploys a limitting receiverr. Host boaard designerrs usingg an EDC PHY IC shouuld follow thhe IC manuufacturers reecommendedd settings foor interooperating the host-boardd EDC PHYY with a limmiting receivver SFP+ moodule. Digitaal diagnnostics functtions are avvailable via a 2-wire seerial interfacce, as speciified in SFFF- 44 5 8472 . The transcceiver is RooHS compliaant and lead free per Dirrective 20022/95/EC , annd 6 Finisar Applicatioon Note ANN-2038 . PROODUCT SELLECTION FTLX11671D3BBTL Finiisar Corporatioon - February 22011 Rev. A0 Page 1 FTLXX1671D3BCL SFP+ ER/EWW Preliminary SSpecification February 20111 I. Pin Descrriptions Pin Symbol Name/Deescription RRef. 1 V Transmittter Ground 1 EET 2 T Transmittter Fault 2 FAULT 3 T Transmittter Disable. Laaser output dissabled on high or open. 3 DIS 4 SDA 2-wire Serial Interface Data Line 2 5 SCL 2-wire Serial Interface Clock Line 2 6 MOD ABS Module AAbsent. Grounnded within thee module 2 7 RS0 Rate Seleect 0. 4 8 RX LOS Loss of SSignal indicatioon. Logic 0 inndicates normall operation. 5 9 RS1 Rate Seleect 1. 4 10 V Receiverr Ground 1 EER 11 V Receiverr Ground 1 EER 12 RD- Receiverr Inverted DATTA out. AC Cooupled. 13 RD+ Receiverr Non-inverted DATA out. AAC Coupled. 14 V Receiverr Ground 1 EER 15 V Receiverr Power Supplyy CCR 16 V Transmittter Power Suppply CCT 17 V Transmittter Ground 1 EET 18 TD+ Transmittter Non-Invertted DATA in. AC Coupled. 19 TD- Transmittter Inverted DDATA in. AC CCoupled. 20 V Transmittter Ground 1 EET Notes:: 1. CCircuit ground iis internally isoolated from chaassis ground. 2. T is an opeen collector/draain output, which should be ppulled up with aa 4.7k 10k OOhms resistor on FFAULT thhe host board iff intended for uuse. Pull up vooltage should bee between 2.0VV to Vcc + 0.3VV. A high ouutput indicates a transmitter ffault caused byy either the TXX bias current or the TX outpuut power exxceeding the prreset alarm thresholds. A loww output indicaates normal opeeration. In the llow state, the ouutput is pulled to <0.8V. 3. Laser output dissabled on T >>2.0V or openn, enabled on TT <0.8V. DIS DIS 4. Innternally pulledd down per SFFF-8431 Rev 4.1. 5. LOS is open colllector output. Should be pullled up with 4.77k 10k on hhost board to aa voltage beetween 2.0V annd 3.6V. Logicc 0 indicates noormal operationn logic 1 indiccates loss of siggnal. VeeT 20 1 VVeeT TD- 19 2 TTX Fault TD+ 18 3 TTX Disable VeeT 17 4 SSDA VccT 16 5 SSCL Towards Towaards VccR 15 6 MMOD ABS Bezel ASIIC VeeR 14 7 RRS0 RD+ 13 8 RRX LOS RD- 12 9 RRS1 VeeR 11 10 VVeeR Figure 1. Diagram oof Host Board Connector Bllock Pin Numbbers and Nammes. Finiisar Corporatioon - February 22011 Rev. A0 Page 2