2 Mbit / 4 Mbit (x8) Small-Sector Flash GLS29SF020 / GLS29SF040 GLS29VF020 / GLS29VF040 GLS29SF/VF020 / 0402Mb / 4Mb (x8) Data Sheet Byte-Program, Small-Sector flash memories FEATURES: Organized as 256K x8 / 512K x8 Fast Erase and Byte-Program: Single Voltage Read and Write Operations Sector-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) 4.5-5.5V for GLS29SF020/040 Byte-Program Time: 14 s (typical) 2.7-3.6V for GLS29VF020/040 Chip Rewrite Time: Superior Reliability 4 seconds (typical) for GLS29SF/VF020 Endurance: 100,000 Cycles (typical) 8 seconds (typical) for GLS29SF/VF040 Greater than 100 years Data Retention Automatic Write Timing Low Power Consumption: Internal V Generation PP Active Current: 10 mA (typical) End-of-Write Detection Standby Current: Toggle Bit 30 A (typical) for GLS29SF020/040 Data Polling 1 A (typical) for GLS29VF020/040 TTL I/O Compatibility for GLS29SF020/040 Sector-Erase Capability CMOS I/O Compatibility for GLS29VF020/040 Uniform 128 Byte sectors JEDEC Standard Fast Read Access Time: Flash EEPROM Pinouts and command sets 55 ns for GLS29SF020/040 70 ns for GLS29VF020/040 Packages Available Latched Address and Data 32-lead PLCC 32-lead TSOP (8mm x 14mm) All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The GLS29SF020/040 and GLS29VF020/040 are 256K The GLS29SF020/040 and GLS29VF020/040 devices x8 / 512K x8 CMOS Small-Sector Flash (SSF) manufac- are suited for applications that require convenient and eco- tured with high-performance SuperFlash technology. The nomical updating of program, configuration, or data mem- split-gate cell design and thick-oxide tunneling injector ory. For all system applications, they significantly improve attain better reliability and manufacturability compared with performance and reliability, while lowering power consump- alternate approaches. The GLS29SF020/040 devices tion. They inherently use less energy during Erase and write (Program or Erase) with a 4.5-5.5V power supply. Program than alternative flash technologies. The total The GLS29VF020/040 devices write (Program or Erase) energy consumed is a function of the applied voltage, cur- with a 2.7-3.6V power supply. These devices conform to rent, and time of application. Since for any given voltage JEDEC standard pin assignments for x8 memories. range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy con- Featuring high performance Byte-Program, the sumed during any Erase or Program operation is less than GLS29SF020/040 and GLS29VF020/040 devices pro- alternative flash technologies. They also improve flexibility vide a maximum Byte-Program time of 20 sec. To protect while lowering the cost for program, data, and configuration against inadvertent write, they have on-chip hardware and storage applications. Software Data Protection schemes. Designed, manufac- tured, and tested for a wide spectrum of applications, these The SuperFlash technology provides fixed Erase and Pro- devices are offered with a guaranteed endurance of at gram times independent of the number of Erase/Program least 10,000 cycles. Data retention is rated at greater than cycles that have occurred. Therefore, the system software 100 years. or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. 2010 Greenliant Systems, Ltd. www.greenliant.com S71160-15-00005/102 Mbit / 4 Mbit Small-Sector Flash GLS29SF020 / GLS29SF040 GLS29VF020 / GLS29VF040 Data Sheet To meet high density, surface mount requirements, the Sector-Erase Operation GLS29SF020/040 and GLS29VF020/040 devices are The Sector-Erase operation allows the system to erase the offered in 32-lead PLCC and 32-lead TSOP packages. The device on a sector-by-sector basis. The GLS29SF020/ pin assignments are shown in Figures 2 and 3. 040 and GLS29VF020/040 offer Sector-Erase mode. The sector architecture is based on uniform sector size of 128 Device Operation Bytes. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase com- Commands are used to initiate the memory operation func- mand (20H) and sector address (SA) in the last bus cycle. tions of the device. Commands are written to the device The sector address is latched on the falling edge of the using standard microprocessor write sequences. A com- sixth WE pulse, while the command (20H) is latched on mand is written by asserting WE low while keeping CE the rising edge of the sixth WE pulse. The internal Erase low. The address bus is latched on the falling edge of WE operation begins after the sixth WE pulse. The End-of- or CE , whichever occurs last. The data bus is latched on Erase operation can be determined using either Data the rising edge of WE or CE , whichever occurs first. Polling or Toggle Bit methods. For timing waveforms, see Figure 9. Any commands issued during the Sector-Erase Read operation are ignored. The Read operation of the GLS29SF020/040 and GLS29VF020/040 devices are controlled by CE and Chip-Erase Operation OE , both have to be low for the system to obtain data The GLS29SF020/040 and GLS29VF020/040 devices from the outputs. CE is used for device selection. When provide a Chip-Erase operation, which allows the user to CE is high, the chip is deselected and only standby power erase the entire memory array to the 1s state. This is use- is consumed. OE is the output control and is used to gate ful when the entire device must be quickly erased. data from the output pins. The data bus is in high imped- ance state when either CE or OE is high. Refer to the The Chip-Erase operation is initiated by executing a six- Read cycle timing diagram in Figure 4 for further details. byte Software Data Protection command sequence with Chip-Erase command (10H) with address 555H in the last Byte-Program Operation byte sequence. The internal Erase operation begins with the rising edge of the sixth WE or CE , whichever occurs The GLS29SF020/040 and GLS29VF020/040 devices first. During the internal Erase operation, the only valid read are programmed on a byte-by-byte basis. Before program- is Toggle Bit or Data Polling. See Table 4 for the com- ming, the sector where the byte exists must be fully erased. mand sequence, Figure 10 for the timing diagram, and Fig- The Program operation is accomplished in three steps. ure 19 for the flowchart. Any commands written during the The first step is the three-byte load sequence for Software Chip-Erase operation will be ignored. Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the Write Operation Status Detection addresses are latched on the falling edge of either CE or WE , whichever occurs last. The data is latched on the ris- The GLS29SF020/040 and GLS29VF020/040 devices ing edge of either CE or WE , whichever occurs first. The provide two software means to detect the completion of a third step is the internal Program operation which is initi- Write (Program or Erase) cycle, in order to optimize the ated after the rising edge of the fourth WE or CE , which- system Write cycle time. The software detection includes ever occurs first. The Program operation, once initiated, will two status bits: Data Polling (DQ ) and Toggle Bit 7 be completed, within 20 s. See Figures 5 and 6 for WE (DQ ). The End-of-Write detection mode is enabled after 6 and CE controlled Program operation timing diagrams the rising edge of WE which initiates the internal Pro- and Figure 16 for flowcharts. During the Program opera- gram or Erase operation. tion, the only valid reads are Data Polling and Toggle Bit. The actual completion of the nonvolatile write is asyn- During the internal Program operation, the host is free to chronous with the system therefore, either a Data Poll- perform additional tasks. Any commands written during the ing or Toggle Bit read may be simultaneous with the internal Program operation will be ignored. completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ . In order to pre- 7 6 2010 Greenliant Systems, Ltd. S71160-15-000 05/10 2