32 Mbit (x8/x16) Concurrent SuperFlash GLS36VF3203 / GLS36VF3204 GLS36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash Data Sheet FEATURES: Organized as 2M x16 or 4M x8 Block-Erase Capability Dual Bank Architecture for Concurrent Uniform 32 KWord blocks Read/Write Operation Erase-Suspend / Erase-Resume Capabilities 32 Mbit Bottom Sector Protection Security ID Feature (in the smaller bank) Greenliant: 128 bits - GLS36VF3203: 8 Mbit + 24 Mbit User: 256 Bytes 32 Mbit Top Sector Protection Fast Read Access Time (in the smaller bank) - GLS36VF3204: 24 Mbit + 8 Mbit 70 ns Single 2.7-3.6V for Read and Write Operations Latched Address and Data Superior Reliability Fast Erase and Program (typical): Endurance: 100,000 cycles (typical) Sector-Erase Time: 18 ms Greater than 100 years Data Retention Block-Erase Time: 18 ms Chip-Erase Time: 35 ms Low Power Consumption: Program Time: 7 s Active Current: 6 mA typical Automatic Write Timing Standby Current: 4 A typical Auto Low Power Mode: 4 A typical Internal V Generation PP Hardware Sector Protection/WP Input Pin End-of-Write Detection Protects 8 KWord in the smaller bank by driving Toggle Bit WP low and unprotects by driving WP high Data Polling Ready/Busy pin Hardware Reset Pin (RST ) CMOS I/O Compatibility Resets the internal state machine to reading array data Conforms to Common Flash Memory Interface (CFI) Byte Pin JEDEC Standards Selects 8-bit or 16-bit mode Flash EEPROM Pinouts and command sets Sector-Erase Capability Packages Available Uniform 2 KWord sectors 48-ball TFBGA (6mm x 8mm) 48-lead TSOP (12mm x 20mm) Chip-Erase Capability PRODUCT DESCRIPTION The GLS36VF320x are 2M x16 or 4M x8 CMOS Concur- ware Data Protection schemes. Designed, manufactured, rent Read/Write Flash Memory manufactured with high and tested for a wide spectrum of applications, these performance SuperFlash technology. The split-gate cell devices are offered with a guaranteed endurance of 10,000 design and thick-oxide tunneling injector attain better reli- cycles. Data retention is rated at greater than 100 years. ability and manufacturability compared with alternate These devices are suited for applications that require con- approaches. The devices write (Program or Erase) with a venient and economical updating of program, configura- 2.7-3.6V power supply and conform to JEDEC standard tion, or data memory. For all system applications, the pinouts for x8/x16 memories. devices significantly improve performance and reliability, Featuring high performance Word-Program, these devices while lowering power consumption. Since for any given provide a typical Program time of 7 sec and use the Tog- voltage range, the SuperFlash technology uses less cur- gle Bit, Data Polling, or RY/BY to detect the completion rent to program and has a shorter erase time, the total of the Program or Erase operation. To protect against inad- energy consumed during any Erase or Program operation vertent write, the devices have on-chip hardware and Soft- 2010 Greenliant Systems, Ltd. www.greenliant.com S71270-05-000 05/1032 Mbit Concurrent SuperFlash GLS36VF3203 / GLS36VF3204 Data Sheet is less than alternative flash technologies. These devices Concurrent Read/Write Operation also improve flexibility while lowering the cost for program, The dual bank architecture of these devices allows the data, and configuration storage applications. Concurrent Read/Write operation whereby the user can SuperFlash technology provides fixed Erase and Program read from one bank while programming or erasing in the times, independent of the number of Erase/Program other bank. For example, reading system code in one bank cycles that have occurred. Therefore the system software while updating data in the other bank. or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Concurrent Read/Write State Erase and Program times increase with accumulated Bank 1 Bank 2 Erase/Program cycles. Read No Operation To meet high-density, surface-mount requirements, these Read Write devices are offered in 48-ball TFBGA and 48-lead TSOP Write Read packages. See Figures 2 and 3 for pin assignments. Write No Operation No Operation Read Device Operation No Operation Write Memory operation functions are initiated using standard Note: For the purposes of this table, write means to perform Block- microprocessor write sequences. A command is written by or Sector-Erase or Program operations as applicable to the asserting WE low while keeping CE low. The address appropriate bank. bus is latched on the falling edge of WE or CE , which- ever occurs last. The data bus is latched on the rising edge Read Operation of WE or CE , whichever occurs first. The Read operation is controlled by CE and OE both have to be low for the system to obtain data from the out- Auto Low Power Mode puts. CE is used for device selection. When CE is high, These devices also have the Auto Lower Power mode the chip is deselected and only standby power is con- which puts them in a near standby mode within 500 ns after sumed. OE is the output control and is used to gate data data has been accessed with a valid Read operation. This from the output pins. The data bus is in a high impedance reduces the I active Read current to 4 A typically. While DD state when either CE or OE is high. Refer to the Read CE is low, the devices exit Auto Low Power mode with cycle timing diagram for further details (Figure 4). any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Program Operation These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the BYTE pin. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either CE or WE , whichever occurs last. The data is latched on the rising edge of either CE or WE , whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE or CE , which- 2010 Greenliant Systems, Ltd. S71270-05-000 05/10 2