1 Mbit / 2 Mbit / 4 Mbitsn(x8) Many-Time Programmable Flash GLS37VF010 / GLS37VF020 / GLS37VF040 GLS37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories Data Sheet FEATURES: Organized as 128K x8 / 256K x8 / 512K x8 Fast Byte-Program Operation: 2.7-3.6V Read Operation Byte-Program Time: 15 s (typical) Chip Program Time: Superior Reliability 2 seconds (typical) for GLS37VF010 Endurance: At least 1000 Cycles 4 seconds (typical) for GLS37VF020 Greater than 100 years Data Retention 8 seconds (typical) for GLS37VF040 Low Power Consumption: Electrical Erase Using Programmer Active Current: 10 mA (typical) Does not require UV source Standby Current: 2 A (typical) Chip-Erase Time: 100 ms (typical) Fast Read Access Time: CMOS I/O Compatibility 70 ns JEDEC Standard Byte-wide Flash Latched Address and Data EEPROM Pinouts Packages Available 32-lead PLCC 32-lead TSOP (8mm x 14mm) 32-pin PDIP Non-Pb (lead-free) packages available PRODUCT DESCRIPTION The GLS37VF010/020/040 devices are 128K x8 / 256K x8 To meet surface mount and conventional through hole / 512K x8 CMOS, Many-Time Programmable (MTP), low requirements, the GLS37VF010/020/040 are offered in 32- cost flash, manufactured with high performance Super- lead PLCC, 32-lead TSOP, and 32-pin PDIP packages. Flash technology. The split-gate cell design and thick-oxide See Figures 2, 3, and 4 for pin assignments. tunneling injector attain better reliability and manufacturabil- ity compared with alternate approaches. The Device Operation GLS37VF010/020/040 can be electrically erased and pro- The GLS37VF010/020/040 devices are nonvolatile mem- grammed at least 1000 times using an external program- ory solutions that can be used instead of standard flash mer, e.g., to change the contents of devices in inventory. devices if in-system programmability is not required. It is The GLS37VF010/020/040 have to be erased prior to pro- functionally (Read) and pin compatible with industry stan- gramming. These devices conform to JEDEC standard dard flash products.The device supports electrical Erase pinouts for byte-wide flash memories. operation via an external programmer. Featuring high performance Byte-Program, the GLS37VF010/020/040 provide a typical Byte-Program Read time of 15 s. Designed, manufactured, and tested for a The Read operation of the GLS37VF010/020/040 is con- wide spectrum of applications, these devices are offered trolled by CE and OE . Both CE and OE have to be with an endurance of at least 1000 cycles. Data retention is low for the system to obtain data from the outputs. Once rated at greater than 100 years. the address is stable, the address access time is equal to The GLS37VF010/020/040 are suited for applications that the delay from CE to output (T ). Data is available at the CE require infrequent writes and low power nonvolatile stor- output after a delay of TOE from the falling edge of OE , age. These devices will improve flexibility, efficiency, and assuming the CE pin has been low and the addresses performance while matching the low cost in nonvolatile have been stable for at least T -T When the CE pin is CE OE. applications that currently use UV-EPROMs, OTPs, and high, the chip is deselected and a standby current of only 2 mask ROMs. A (typical) is consumed. OE is the output control and is 2010 Greenliant Systems, Ltd. www.greenliant.com S71151-11-000 05/101 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash GLS37VF010 / GLS37VF020 / GLS37VF040 Data Sheet used to gate data from the output pins. The data bus is in Product Identification Mode high impedance state when either CE or OE is V IH. The Product Identification mode identifies the devices as Refer to Figure 5 for the timing diagram. GLS37VF010, GLS37VF020, and GLS37VF040 and man- ufacturer as Greenliant. This mode may be accessed by Byte-Program Operation the hardware method. To activate this mode, the program- ming equipment must force V (11.4-12V) on address A . H 9 The GLS37VF010/020/040 are programmed by using an Two identifier bytes may then be sequenced from the external programmer. The programming mode is activated device outputs by toggling address line A . For details, see 0 by asserting 11.4-12V on OE pin and V on CE pin. The IL Table 3 for hardware operation. device is programmed using a single pulse (WE pin low) of 15 s per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-by-byte until the TABLE 1: Product Identification entire chip has been programmed. Refer to Figure 11 for Address Data the flowchart and Figure 7 for the timing diagram. Manufacturers ID 0000H BFH Device ID Chip-Erase Operation GLS37VF010 0001H C5H The only way to change a data from a 0 to 1 is by GLS37VF020 0001H C6H electrical erase that changes every bit in the device to GLS37VF040 0001H C2H 1. The GLS37VF010/020/040 use an electrical Chip- T1.2 1151 Erase operation. The entire chip can be erased in 100 ms (WE pin low). In order to activate erase mode, the Design Considerations 11.4-12V is applied to OE and A pins while CE is 9 The GLS37VF010/020/040 should have a 0.1 F ceramic low. All other address and data pins are dont care. high frequency, low inductance capacitor connected The falling edge of WE will start the Chip-Erase oper- between V and GND. This capacitor should be placed ation. Once the chip has been erased, all bytes must DD as close to the package terminals as possible. be verified for FFH. Refer to Figure 10 for the flowchart and Figure 6 for the timing diagram. OE and A must remain stable at V for the entire dura- 9 H tion of an Erase operation. OE must remain stable at V H for the entire duration of the Program operation. SuperFlash X-Decoder Memory Memory Address Address Buffer Y-Decoder CE OE I/O Buffers Control Logic A 9 WE DQ - DQ 7 0 1151 B1.1 FIGURE 1: Functional Block Diagram 2010 Greenliant Systems, Ltd. S71151-11-000 05/10 2