GLS85LP1002A / 1004B / 1008B / 1016B / 1032A Industrial / Commercial Temp PATA N ANDr i ve Fact Sheet 03.001 February 2014 Features Industry Standard ATA / IDE Bus Interface Expanded Data Protection - Host Interface: 16-bit access - WP /PD pin configurable by firmware for - Supports 48-bit address feature set prevention of data overwrites 1) - Data security through user-selectable - Supports up to PIO Mode-6 2) protection zones - Supports up to Multi-Word DMA Mode-4 - Security Erase feature - Supports up to Ultra DMA Mode-6 Integrated Voltage Detector Performance - Prevents inadvertent Write operations due to - Sequential data read: unexpected power-down or brownout Up to 60 MByte/sec 20-Byte Unique ID for Enhanced Security - Sequential data write: - Factory pre-programmed 10-Byte unique ID Up to 30 MByte/sec - User-programmable 10-Byte ID Power Management NAND Configuration - 3.3V power supply - 2 bits per cell (MLC) - Immediate disabling of unused circuitry Temperature Range without host intervention - Zero wake-up latency - Commercial: 0C to 70C Power Specification - Industrial: -40C to 85C 4) 91-ball BGA and LBGA Package - Active mode 150mA typical (GLS85LP1032A) - 14mm x 24mm x 1.90mm, 1mm ball pitch, FTE 140mA typical (GLS85LP1016B) (4 GB, 8 GB, 16 GB, 32 GB) 100mA typical (GLS85LP1008B) - 14mm x 24mm x 1.45mm, 1mm ball pitch, LFTE 60mA typical (GLS85LP1004B) (4 GB, 8 GB) Note: Devices using LFTE are not 60mA typical (GLS85LP1002A) recommended for new designs. - Sleep mode - 12mm x 24mm x 1.40mm, 1mm ball pitch, LBTE 500A typical (2 GB) Supports SMART Commands All Devices are RoHS Compliant Robust Built-in ECC Product Description The GLS85LP1002A / 1004B / 1008B / 1016B / 1032A The integrated NAND flash controller with built-in Industrial and Commercial Temp PATA NANDrive advanced NAND management firmware communicates devices (referred to as PATA NANDrive in this fact with the host through the standard ATA protocol. It does sheet) are high-performance, fully integrated solid state not require any additional or proprietary software such as drives. They combine a Greenliant NAND controller and 2, the Flash File System (FFS) and Memory Technology 4, 8, 16 or 32 GByte of NAND flash memory in a multi- Driver (MTD). chip package. These products are ideal for embedded PATA NANDrive provides a WP /PD pin to protect and portable applications that require smaller form factor critical information stored in the flash media from and more reliable data storage. unauthorized overwrites. PATA NANDrive is pre- ATA-based solid state mass storage technology is widely programmed with a 10-Byte unique serial ID and has the used in GPS and telematics, in-vehicle infotainment, option of programming an additional 10-Byte serial ID for portable and industrial computers, handheld data even greater system security. collection scanners, point-of-sale terminals, networking PATA NANDrives advanced NAND management and telecommunications equipment, robotics, audio and technology enhances data security, improves endurance video recorders, monitoring devices and set-top boxes. and accurately predicts the remaining life of the NAND PATA NANDrive supports standard ATA/IDE protocol with flash devices. This innovative technology combines robust up to PIO Mode-61), Multi-Word DMA Mode-42) and Ultra error correction capabilities with advanced wear-leveling DMA Mode-6 interface. PATA NANDrive provides algorithms and bad block management to significantly complete IDE hard disk drive functionality and extend the life of the product. compatibility in a 14mm x 24mm BGA package or a 1) PATA NANDrive is capable of supporting PIO Mode-6, but Identify-Drive information report will show PIO Mode-4 12mm x 24mm LBGA package for easy, space saving 2) PATA NANDrive is capable of supporting Multi-Word DMA mounting to a system motherboard. These products Mode-4, but Identify-Drive information report will show surpass traditional storage in their small size, security, MWDMA Mode-2 reliability, ruggedness and low power consumption. These specifications are subject to change without notice. 02/21/2014 2014 Greenliant Systems 1 S71441-F GLS85LP1002A / 1004B / 1008B / 1016B / 1032A Industrial / Commercial Temp PATA N ANDr i ve Fact Sheet 03.001 February 2014 1.0 GENERAL DESCRIPTION Each PATA NANDrive contains an integrated PATA NAND flash memory controller and NAND flash die in a BGA or LBGA package. Refer to Figure 2-1 for the PATA NANDrive block diagram. 1.1.5 Error Correction Code (ECC) 1.1 Optimized PATA NANDrive High performance is achieved through optimized The heart of PATA NANDrive is the PATA NAND flash hardware error detection and correction. memory controller, which translates standard PATA signals into flash media data and control signals. The 1.1.6 Serial Communication Interface (SCI) following components contribute to PATA NANDrives The Serial Communication Interface (SCI) is designed operation. for error reporting. During the product development stage, it is recommended to provide the SCI port on 1.1.1 Microcontroller Unit (MCU) the PCB to aid in design validation. The MCU transfers the ATA/IDE commands into data and control signals required for flash media operation. 1.1.7 Multi-tasking Interface 1.1.2 Internal Direct Memory Access (DMA) The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read, PATA NANDrive uses internal DMA allowing instant Program and Erase operations to multiple flash media. data transfer from/to buffer to/from flash media. This implementation eliminates microcontroller overhead associated with the traditional, firmware-based 1.2 SMT Reflow Consideration approach, thereby increasing the data transfer rate. The PATA NANDrive family utilizes standard NAND 1.1.3 Power Management Unit (PMU) flash for data storage. Because the high temperature in a surface-mount soldering reflow process can alter The PMU controls the power consumption of PATA the content on NAND flash, do not program PATA NANDrive. The PMU dramatically reduces the power NANDrive before the reflow process. consumption of PATA NANDrive by putting the part of the circuitry that is not in operation into sleep mode. 1.3 Advanced NAND Management The Flash File System handles inadvertent power interrupts and has auto-recovery capability to ensure PATA NANDrives integrated controller uses PATA NANDrives data integrity. For regular power advanced wear-leveling algorithms to substantially management, the host must send an increase the longevity of NAND flash media. Wear IDLE IMMEDIATE command and wait for command caused by data writes is evenly distributed in all or ready before powering down PATA NANDrive. select blocks in the device that prevents hot spots in locations that are programmed and erased extensively. 1.1.4 Embedded Flash File System This effective wear-leveling technique results in The embedded flash file system is an integral part of optimized device endurance, enhanced data retention PATA NANDrive. It contains MCU firmware that and higher reliability required by long-life applications. performs the following tasks: 1. Translates host side signals into flash media writes and reads 2. Provides flash media wear leveling to spread the flash writes across all memory address space to increase the longevity of flash media 3. Keeps track of data file structures 4. Manages system security for the selected protection zones 5. Stores the data in flash media upon completion of a Write command (PATA NANDrive does not perform Post-Write operations, except for when the write cache is enabled) These specifications are subject to change without notice. 02/21/2014 2014 Greenliant Systems 2 S71441-F