GLS85LP0512P / 1002P / 1004P / 1008P Industrial Grade PATA NANDrive Fact Sheet 03.000 February 2014 Features Industry Standard ATA / IDE Bus Interface Expanded Data Protection - Host Interface: 16-bit access - WP /PD pin configurable by firmware for - Supports 48-bit address feature set prevention of data overwrites 1) - Data security through user-selectable protection - Supports up to PIO Mode-6 2) zones - Supports up to Multi-Word DMA Mode-4 - Security Erase feature - Supports up to Ultra DMA Mode-6 Integrated Voltage Detector Performance - Prevents inadvertent Write operations due to - Sequential data read: unexpected power-down or brownout Up to 50 MByte/sec 20-Byte Unique ID for Enhanced Security - Sequential data write: - Factory pre-programmed 10-Byte unique ID Up to 35 MByte/sec - User-programmable 10-Byte ID Power Management Robust Built-in ECC - 3.3V power supply - Immediate disabling of unused circuitry without NAND Configuration host intervention - 1 bit per cell (SLC) - Zero wake-up latency Temperature Range Power Specification - Industrial: -40C to 85C - Active mode 91-ball BGA and LBGA Packages 100mA typical (GLS85LP1008P) - 14mm x 24mm x 1.90mm, 1mm ball pitch, FTE 80mA typical (GLS85LP1004P) (2GB, 4GB, 8GB) 60mA typical (GLS85LP1002P/0512P) - 12mm x 24mm x 1.40mm, 1mm ball pitch, LBTE - Sleep mode (512MB) 500A typical All Devices are RoHS Compliant Supports SMART Commands Product Description The GLS85LP0512P / 1002P / 1004P / 1008P The integrated NAND flash controller with built-in Industrial Grade PATA NANDrive devices (referred advanced NAND management firmware to as PATA NANDrive in this fact sheet) are high- communicates with the host through the standard ATA performance, fully integrated solid state drives. They protocol. It does not require any additional or combine a Greenliant NAND controller and 512 MByte, proprietary software such as the Flash File System 2 GByte, 4 GByte or 8 GByte of NAND flash memory (FFS) and Memory Technology Driver (MTD). in a multi-chip package. These products are ideal for PATA NANDrive provides a WP /PD pin to protect embedded and portable applications that require critical information stored in the flash media from smaller form factor and more reliable data storage. unauthorized overwrites. PATA NANDrive is pre- programmed with a 10-Byte unique serial ID and has ATA-based solid state mass storage technology is the option of programming an additional 10-Byte serial widely used in GPS and telematics, in-vehicle ID for even greater system security. infotainment, portable and industrial computers, handheld data collection scanners, point-of-sale PATA NANDrives advanced NAND management terminals, networking and telecommunications technology enhances data security, improves equipment, robotics, audio and video recorders, endurance and accurately predicts the remaining monitoring devices and set-top boxes. lifespan of the NAND flash devices. This innovative technology combines robust error correction PATA NANDrive supports standard ATA/IDE protocol capabilities with advanced wear-leveling algorithms 1) 2) with up to PIO Mode-6 , Multi-Word DMA Mode-4 and bad block management to significantly extend the and Ultra DMA Mode-6 interface. The PATA life of the product. NANDrive device provides complete IDE hard disk 1) PATA NANDrive is capable of supporting PIO Mode-6, drive functionality and compatibility in a 14mm x but Identify-Drive information report will show PIO Mode-4 24mm BGA package or a 12mm x 24mm LBGA 2) PATA NANDrive is capable of supporting Multi-Word package for easy, space saving mounting to a system DMA Mode-4, but Identify-Drive information report will show MWDMA Mode-2 motherboard. These products surpass traditional storage in their small size, security, reliability, ruggedness and low power consumption. These specifications are subject to change without notice. 02/19/2014 2014 Greenliant Systems 1 S71431-F GLS85LP0512P / 1002P / 1004P / 1008P Industrial Grade PATA NANDrive Fact Sheet 03.000 February 2014 1.0 GENERAL DESCRIPTION Each PATA NANDrive contains an integrated PATA NAND flash memory controller and NAND flash die in a BGA or LBGA package. Refer to Figure 2-1 for the PATA NANDrive block diagram. 1.1 Optimized PATA NANDrive 1.1.5 Error Correction Code (ECC) The heart of PATA NANDrive is the PATA NAND flash High performance is achieved through optimized memory controller, which translates standard PATA hardware error detection and correction. signals into flash media data and control signals. The following components contribute to PATA NANDrives 1.1.6 Serial Communication Interface (SCI) operation. The Serial Communication Interface (SCI) is designed 1.1.1 Microcontroller Unit (MCU) for error reporting. During the product development stage, it is recommended to provide the SCI port on The MCU transfers the ATA/IDE commands into data the PCB to aid in design validation. and control signals required for flash media operation. 1.1.2 Internal Direct Memory Access (DMA) 1.1.7 Multi-tasking Interface PATA NANDrive uses internal DMA allowing instant The multi-tasking interface enables fast, sustained data transfer from/to buffer to/from flash media. This write performance by allowing concurrent Read, implementation eliminates microcontroller overhead Program and Erase operations to multiple flash media. associated with the traditional, firmware-based 1.2 SMT Reflow Consideration approach, thereby increasing the data transfer rate. The PATA NANDrive family utilizes standard NAND 1.1.3 Power Management Unit (PMU) flash for data storage. Because the high temperature The PMU controls the power consumption of PATA in a surface-mount soldering reflow process can alter NANDrive. The PMU dramatically reduces the power the content on NAND flash, do not program PATA consumption of PATA NANDrive by putting the part of NANDrive before the reflow process. the circuitry that is not in operation into sleep mode. 1.3 Advanced NAND Management The Flash File System handles inadvertent power interrupts and has auto-recovery capability to ensure PATA NANDrives integrated controller uses PATA NANDrives data integrity. For regular power advanced wear-leveling algorithms to substantially management, the host must send an increase the longevity of NAND flash media. Wear IDLE IMMEDIATE command and wait for command caused by data writes is evenly distributed in all or ready before powering down PATA NANDrive. select blocks in the device that prevents hot spots in locations that are programmed and erased extensively. 1.1.4 Embedded Flash File System This effective wear-leveling technique results in The embedded flash file system is an integral part of optimized device endurance, enhanced data retention PATA NANDrive. It contains MCU firmware that and higher reliability required by long-life applications. performs the following tasks: 1. Translates host side signals into flash media writes and reads 2. Provides flash media wear leveling to spread the flash writes across all memory address space to increase the longevity of flash media 3. Keeps track of data file structures 4. Manages system security for the selected protection zones 5. Stores the data in flash media upon completion of a Write command (PATA NANDrive does not perform Post-Write operations, except for when the write cache is enabled) These specifications are subject to change without notice. 02/19/2014 2014 Greenliant Systems 2 S71431-F